From 31b2c3ea7a21a45c975bc6847c39b82d3c458af2 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Sat, 29 Feb 2020 13:07:32 -0500 Subject: [PATCH] stm32: Fix broken clock setup on stm32f1 Commit bd6c25c9 introduced a typo that caused the clock divisors to not be set correctly on stm32f1. Reported by @brianrjones69. Signed-off-by: Kevin O'Connor --- src/stm32/stm32f1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stm32/stm32f1.c b/src/stm32/stm32f1.c index 66c4933bd..bb07d3402 100644 --- a/src/stm32/stm32f1.c +++ b/src/stm32/stm32f1.c @@ -140,8 +140,8 @@ clock_setup(void) cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) | ((div2 - 2) << RCC_CFGR_PLLMULL_Pos)); } - RCC->CFGR = (cfgr | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 - | RCC_CFGR_ADCPRE_DIV4); + cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV4; + RCC->CFGR = cfgr; RCC->CR |= RCC_CR_PLLON; // Set flash latency