From 90ffa0685f368d00a76f9b7746315aa3b3a5f1ec Mon Sep 17 00:00:00 2001
From: Arkadiusz Raj <arek@raj.priv.pl>
Date: Fri, 19 Feb 2021 16:42:27 +0000
Subject: [PATCH] stm32: stm32f401 pll_freq updates
Signed-off-by: Arkadiusz Raj <arek.raj@gmail.com>
---
src/stm32/stm32f4.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c
index e6f8637fa..dc7a15aae 100644
--- a/src/stm32/stm32f4.c
+++ b/src/stm32/stm32f4.c
@@ -146,7 +146,8 @@ enable_clock_stm32f40x(void)
#if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 \
|| CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F429
uint32_t pll_base = (CONFIG_STM32_CLOCK_REF_25M) ? 1000000 : 2000000;
- uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
+ uint32_t pllp = (CONFIG_MACH_STM32F401) ? 4 : 2;
+ uint32_t pll_freq = CONFIG_CLOCK_FREQ * pllp, pllcfgr;
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
// Configure 168Mhz PLL from external crystal (HSE)
uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
@@ -158,7 +159,7 @@ enable_clock_stm32f40x(void)
pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
}
RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
- | (0 << RCC_PLLCFGR_PLLP_Pos)
+ | (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_Pos)
| ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos));
RCC->CR |= RCC_CR_PLLON;
#endif