smark- eedc773d69 stm32f1: Fix ADC (#1474)
The sampling time of the ADC was too slow (239 ADC clock cycles), causing the reading of the next ADC channel to have cross talk as per issue #1261. Sampling time updated to 41 ADC clock cycles.

Signed-off-by: Marco D'Alessio <marco@wrecklab.com>
2019-03-31 14:32:27 -04:00
..
2019-03-31 14:32:27 -04:00
2019-03-11 22:33:24 -04:00
2019-02-27 14:20:15 -05:00
2019-02-27 14:20:15 -05:00