f1982edcd5
Load the interrupt vector table into ram at startup. This reduces the chance of a flash cache access causing timing instability. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
82 lines
1.9 KiB
ArmAsm
82 lines
1.9 KiB
ArmAsm
// rp2040 linker script (based on armcm_link.lds.S and customized for stage2)
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//
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// Copyright (C) 2019-2024 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_FLASH_SIZE
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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#if CONFIG_RP2040_HAVE_STAGE2
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#define ROM_ORIGIN 0x10000000
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#else
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#define ROM_ORIGIN CONFIG_FLASH_APPLICATION_ADDRESS
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#endif
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MEMORY
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{
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rom (rx) : ORIGIN = ROM_ORIGIN , LENGTH = CONFIG_FLASH_SIZE
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ram (rwx) : ORIGIN = CONFIG_RAM_START , LENGTH = CONFIG_RAM_SIZE
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}
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SECTIONS
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{
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.text : {
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. = ALIGN(4);
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#if CONFIG_RP2040_HAVE_STAGE2
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KEEP(*(.boot2))
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#endif
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_text_vectortable_start = .;
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KEEP(*(.vector_table))
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_text_vectortable_end = .;
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*(.text.armcm_boot*)
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} > rom
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. = ALIGN(4);
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_data_flash = .;
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.ram_vectortable (NOLOAD) : {
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_ram_vectortable_start = .;
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. = . + ( _text_vectortable_end - _text_vectortable_start ) ;
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_ram_vectortable_end = .;
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} > ram
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.data : AT (_data_flash)
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{
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. = ALIGN(4);
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_data_start = .;
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*(.text .text.*)
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*(.ramfunc .ramfunc.*);
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*(.rodata .rodata*)
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*(.data .data.*);
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. = ALIGN(4);
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_data_end = .;
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} > ram
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_bss_start = .;
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4);
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_bss_end = .;
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} > ram
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_stack_start = CONFIG_RAM_START + CONFIG_RAM_SIZE - CONFIG_STACK_SIZE ;
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.stack _stack_start (NOLOAD) :
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{
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. = . + CONFIG_STACK_SIZE;
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_stack_end = .;
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} > ram
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/DISCARD/ : {
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// The .init/.fini sections are used by __libc_init_array(), but
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// that isn't needed so no need to include them in the binary.
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*(.init)
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*(.fini)
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}
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}
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