commit 9a13d65e168efc188c0817b937d93ef0b05eef46
Author: 徐青宇 <10510612+xu-qingyuxx@user.noreply.gitee.com>
Date: Mon Apr 10 15:48:01 2023 +0800
实现kill按键外部中断 对p10-p12的开关
diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..b0a6341
--- /dev/null
+++ b/.vscode/c_cpp_properties.json
@@ -0,0 +1,39 @@
+{
+ "configurations": [
+ {
+ "name": "Target 1",
+ "includePath": [
+ "d:\\Users\\User\\Documents\\peek250kill control\\myinc",
+ "D:\\Keil_v5\\C51\\INC",
+ "d:\\Users\\User\\Documents\\peek250kill control",
+ "d:\\Users\\User\\Documents\\peek250kill control\\mycode"
+ ],
+ "defines": [
+ "__C51__",
+ "__VSCODE_C51__",
+ "reentrant=",
+ "compact=",
+ "small=",
+ "large=",
+ "data=",
+ "idata=",
+ "pdata=",
+ "bdata=",
+ "xdata=",
+ "code=",
+ "bit=char",
+ "sbit=char",
+ "sfr=char",
+ "sfr16=int",
+ "sfr32=int",
+ "interrupt=",
+ "using=",
+ "_at_=",
+ "_priority_=",
+ "_task_="
+ ],
+ "intelliSenseMode": "${default}"
+ }
+ ],
+ "version": 4
+}
\ No newline at end of file
diff --git a/.vscode/keil-assistant.log b/.vscode/keil-assistant.log
new file mode 100644
index 0000000..be2a400
--- /dev/null
+++ b/.vscode/keil-assistant.log
@@ -0,0 +1,8 @@
+[info] Log at : 2023/4/10|15:03:01|GMT+0800
+
+[info] Log at : 2023/4/10|15:03:11|GMT+0800
+
+[info] Log at : 2023/4/10|15:46:14|GMT+0800
+
+[info] Log at : 2023/4/10|15:46:58|GMT+0800
+
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 0000000..26f6d05
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,9 @@
+{
+ "C_Cpp.errorSquiggles": "disabled",
+ "files.associations": {
+ "timer.h": "c",
+ "exti.h": "c",
+ "gpio.h": "c",
+ "config.h": "c"
+ }
+}
\ No newline at end of file
diff --git a/.vscode/uv4.log b/.vscode/uv4.log
new file mode 100644
index 0000000..7c98c7b
--- /dev/null
+++ b/.vscode/uv4.log
@@ -0,0 +1,10 @@
+Build target 'Target 1'
+compiling Exti.c...
+compiling GPIO.c...
+compiling main.c...
+compiling timer.c...
+linking...
+Program Size: data=18.0 xdata=0 code=2183
+creating hex file from ".\Objects\kill_control"...
+".\Objects\kill_control" - 0 Error(s), 0 Warning(s).
+Build Time Elapsed: 00:00:00
diff --git a/.vscode/uv4.log.lock b/.vscode/uv4.log.lock
new file mode 100644
index 0000000..85095db
--- /dev/null
+++ b/.vscode/uv4.log.lock
@@ -0,0 +1 @@
+2023/4/10 15:47:04
\ No newline at end of file
diff --git a/Listings/Exti.lst b/Listings/Exti.lst
new file mode 100644
index 0000000..d21a1f4
--- /dev/null
+++ b/Listings/Exti.lst
@@ -0,0 +1,174 @@
+C51 COMPILER V9.60.0.0 EXTI 04/10/2023 15:47:03 PAGE 1
+
+
+C51 COMPILER V9.60.0.0, COMPILATION OF MODULE EXTI
+OBJECT MODULE PLACED IN .\Objects\Exti.obj
+COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\Exti.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEN
+ -D PRINT(.\Listings\Exti.lst) TABS(2) OBJECT(.\Objects\Exti.obj)
+
+line level source
+
+ 1 /*---------------------------------------------------------------------*/
+ 2 /* --- STC MCU Limited ------------------------------------------------*/
+ 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/
+ 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/
+ 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+ 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+ 7 /* --- Web: www.STCMCU.com --------------------------------------------*/
+ 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+ 9 /* --- QQ: 800003751 -------------------------------------------------*/
+ 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */
+ 11 /*---------------------------------------------------------------------*/
+ 12
+ 13 /************* ˵ **************
+ 14
+ 15 ļΪSTC8ϵежϳʼжϳ,ûļԼҪжϳ.
+ 16
+ 17 ******************************************/
+ 18
+ 19 #include "Exti.h"
+ 20
+ 21 /************* ⲿͱ *****************/
+ 22
+ 23 /********************* INT0жϺ *************************/
+ 24 void Ext_INT0(void) interrupt INT0_VECTOR // жʱѾ־
+ 25 {
+ 26 1 if (kill_gpio)
+ 27 1 {
+ 28 2 if (KILL_time == 0)
+ 29 2 {
+ 30 3 power1_gpio = !power1_gpio;
+ 31 3 power2_gpio = !power2_gpio;
+ 32 3 power3_gpio = !power3_gpio;
+ 33 3 }
+ 34 2 }
+ 35 1 else
+ 36 1 {
+ 37 2 KILL_time = 50;
+ 38 2 }
+ 39 1 }
+ 40
+ 41 /********************* INT1жϺ *************************/
+ 42 void Ext_INT1(void) interrupt INT1_VECTOR // жʱѾ־
+ 43 {
+ 44 1 }
+ 45
+ 46 /********************* INT2жϺ *************************/
+ 47 void Ext_INT2(void) interrupt INT2_VECTOR //
+ 48 {
+ 49 1 }
+ 50
+ 51 /********************* INT3жϺ *************************/
+ 52 void Ext_INT3(void) interrupt INT3_VECTOR
+ 53 {
+ 54 1 }
+ C51 COMPILER V9.60.0.0 EXTI 04/10/2023 15:47:03 PAGE 2
+
+ 55
+ 56 /********************* INT4жϺ *************************/
+ 57 void Ext_INT4(void) interrupt INT4_VECTOR
+ 58 {
+ 59 1 }
+ 60
+ 61 //========================================================================
+ 62 // : u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx)
+ 63 // : ⲿжϳʼ.
+ 64 // : INTx: ṹ,οExti.hĶ.
+ 65 // : ɹ0, ղ1,2.
+ 66 // 汾: V1.0, 2012-10-22
+ 67 //========================================================================
+ 68 u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx)
+ 69 {
+ 70 1 if (EXT > EXT_INT4)
+ 71 1 return 1; // ղ
+ 72 1
+ 73 1 if (EXT == EXT_INT0) // ж0
+ 74 1 {
+ 75 2 IE0 = 0; // ж0־λ
+ 76 2 if (INTx->EXTI_Interrupt == ENABLE)
+ 77 2 EX0 = 1; // ж
+ 78 2 else
+ 79 2 EX0 = 0; // ֹж
+ 80 2 if (INTx->EXTI_Priority > Priority_3)
+ 81 2 return 2; //
+ 82 2 INT0_Priority(INTx->EXTI_Priority); // ָжȼ(͵) Priority_0,Priority_1,Priority_2,Pri
+ -ority_3
+ 83 2 if (INTx->EXTI_Mode == EXT_MODE_Fall)
+ 84 2 IT0 = 1; // ½ж
+ 85 2 else
+ 86 2 IT0 = 0; // ,½ж
+ 87 2 return 0; // ɹ
+ 88 2 }
+ 89 1
+ 90 1 if (EXT == EXT_INT1) // ж1
+ 91 1 {
+ 92 2 IE1 = 0; // ж1־λ
+ 93 2 if (INTx->EXTI_Interrupt == ENABLE)
+ 94 2 EX1 = 1; // ж
+ 95 2 else
+ 96 2 EX1 = 0; // ֹж
+ 97 2 if (INTx->EXTI_Priority > Priority_3)
+ 98 2 return 2; //
+ 99 2 INT1_Priority(INTx->EXTI_Priority); // ָжȼ(͵) Priority_0,Priority_1,Priority_2,Pri
+ -ority_3
+ 100 2 if (INTx->EXTI_Mode == EXT_MODE_Fall)
+ 101 2 IT1 = 1; // ½ж
+ 102 2 else
+ 103 2 IT1 = 0; // ,½ж
+ 104 2 return 0; // ɹ
+ 105 2 }
+ 106 1
+ 107 1 if (EXT == EXT_INT2) // ж2, ̶Ϊ½صȼж
+ 108 1 {
+ 109 2 if (INTx->EXTI_Interrupt == ENABLE)
+ 110 2 INT_CLKO |= (1 << 4); // ж
+ 111 2 else
+ 112 2 INT_CLKO &= ~(1 << 4); // ֹж
+ 113 2 return 0; // ɹ
+ 114 2 }
+ C51 COMPILER V9.60.0.0 EXTI 04/10/2023 15:47:03 PAGE 3
+
+ 115 1
+ 116 1 if (EXT == EXT_INT3) // ж3, ̶Ϊ½صȼж
+ 117 1 {
+ 118 2 if (INTx->EXTI_Interrupt == ENABLE)
+ 119 2 INT_CLKO |= (1 << 5); // ж
+ 120 2 else
+ 121 2 INT_CLKO &= ~(1 << 5); // ֹж
+ 122 2 return 0; // ɹ
+ 123 2 }
+ 124 1
+ 125 1 if (EXT == EXT_INT4) // ж4, ̶Ϊ½صȼж
+ 126 1 {
+ 127 2 if (INTx->EXTI_Interrupt == ENABLE)
+ 128 2 INT_CLKO |= (1 << 6); // ж
+ 129 2 else
+ 130 2 INT_CLKO &= ~(1 << 6); // ֹж
+ 131 2 return 0; // ɹ
+ 132 2 }
+ 133 1 return 2; // ʧ
+ 134 1 }
+ 135 void Exti_config(void)
+ 136 {
+ 137 1 EXTI_InitTypeDef Exti_InitStructure; // ṹ
+ 138 1
+ 139 1 Exti_InitStructure.EXTI_Interrupt = ENABLE; // жʹ, ENABLEDISABLE
+ 140 1 Exti_InitStructure.EXTI_Mode = EXT_MODE_RiseFall; // жģʽ, EXT_MODE_RiseFall,EXT_MODE_Fall
+ 141 1 Exti_InitStructure.EXTI_Priority = Priority_0; // ָжȼ(͵) Priority_0,Priority_1,Prio
+ -rity_2,Priority_3
+ 142 1 Ext_Inilize(EXT_INT0, &Exti_InitStructure); // ʼ
+ 143 1 }
+
+
+MODULE INFORMATION: STATIC OVERLAYABLE
+ CODE SIZE = 340 ----
+ CONSTANT SIZE = ---- ----
+ XDATA SIZE = ---- ----
+ PDATA SIZE = ---- ----
+ DATA SIZE = ---- 3
+ IDATA SIZE = ---- ----
+ BIT SIZE = ---- ----
+END OF MODULE INFORMATION.
+
+
+C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
diff --git a/Listings/GPIO.lst b/Listings/GPIO.lst
new file mode 100644
index 0000000..37fa8d2
--- /dev/null
+++ b/Listings/GPIO.lst
@@ -0,0 +1,169 @@
+C51 COMPILER V9.60.0.0 GPIO 04/10/2023 15:47:03 PAGE 1
+
+
+C51 COMPILER V9.60.0.0, COMPILATION OF MODULE GPIO
+OBJECT MODULE PLACED IN .\Objects\GPIO.obj
+COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\GPIO.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEN
+ -D PRINT(.\Listings\GPIO.lst) TABS(2) OBJECT(.\Objects\GPIO.obj)
+
+line level source
+
+ 1 /*---------------------------------------------------------------------*/
+ 2 /* --- STC MCU Limited ------------------------------------------------*/
+ 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/
+ 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/
+ 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+ 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+ 7 /* --- Web: www.STCMCU.com --------------------------------------------*/
+ 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+ 9 /* --- QQ: 800003751 -------------------------------------------------*/
+ 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */
+ 11 /*---------------------------------------------------------------------*/
+ 12
+ 13 /*************** ˵ ****************
+ 14
+ 15 ļΪSTC8ϵеĶ˿ڳʼ,ûԲ.
+ 16
+ 17 ******************************************/
+ 18
+ 19 #include "GPIO.h"
+ 20
+ 21 //========================================================================
+ 22 // : u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx)
+ 23 // : ʼIO.
+ 24 // : GPIOx: ṹ,οtimer.hĶ.
+ 25 // : ɹ0, ղ1,2.
+ 26 // 汾: V1.0, 2012-10-22
+ 27 //========================================================================
+ 28 u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx)
+ 29 {
+ 30 1 if (GPIO > GPIO_P7)
+ 31 1 return 1; // ղ
+ 32 1 if (GPIOx->Mode > GPIO_OUT_PP)
+ 33 1 return 2; //
+ 34 1 if (GPIO == GPIO_P0)
+ 35 1 {
+ 36 2 if (GPIOx->Mode == GPIO_PullUp)
+ 37 2 P0M1 &= ~GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // ˫
+ 38 2 if (GPIOx->Mode == GPIO_HighZ)
+ 39 2 P0M1 |= GPIOx->Pin, P0M0 &= ~GPIOx->Pin; //
+ 40 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 41 2 P0M1 |= GPIOx->Pin, P0M0 |= GPIOx->Pin; // ©
+ 42 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 43 2 P0M1 &= ~GPIOx->Pin, P0M0 |= GPIOx->Pin; //
+ 44 2 }
+ 45 1 if (GPIO == GPIO_P1)
+ 46 1 {
+ 47 2 if (GPIOx->Mode == GPIO_PullUp)
+ 48 2 P1M1 &= ~GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // ˫
+ 49 2 if (GPIOx->Mode == GPIO_HighZ)
+ 50 2 P1M1 |= GPIOx->Pin, P1M0 &= ~GPIOx->Pin; //
+ 51 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 52 2 P1M1 |= GPIOx->Pin, P1M0 |= GPIOx->Pin; // ©
+ 53 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 54 2 P1M1 &= ~GPIOx->Pin, P1M0 |= GPIOx->Pin; //
+ C51 COMPILER V9.60.0.0 GPIO 04/10/2023 15:47:03 PAGE 2
+
+ 55 2 }
+ 56 1 if (GPIO == GPIO_P2)
+ 57 1 {
+ 58 2 if (GPIOx->Mode == GPIO_PullUp)
+ 59 2 P2M1 &= ~GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // ˫
+ 60 2 if (GPIOx->Mode == GPIO_HighZ)
+ 61 2 P2M1 |= GPIOx->Pin, P2M0 &= ~GPIOx->Pin; //
+ 62 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 63 2 P2M1 |= GPIOx->Pin, P2M0 |= GPIOx->Pin; // ©
+ 64 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 65 2 P2M1 &= ~GPIOx->Pin, P2M0 |= GPIOx->Pin; //
+ 66 2 }
+ 67 1 if (GPIO == GPIO_P3)
+ 68 1 {
+ 69 2 if (GPIOx->Mode == GPIO_PullUp)
+ 70 2 P3M1 &= ~GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // ˫
+ 71 2 if (GPIOx->Mode == GPIO_HighZ)
+ 72 2 P3M1 |= GPIOx->Pin, P3M0 &= ~GPIOx->Pin; //
+ 73 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 74 2 P3M1 |= GPIOx->Pin, P3M0 |= GPIOx->Pin; // ©
+ 75 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 76 2 P3M1 &= ~GPIOx->Pin, P3M0 |= GPIOx->Pin; //
+ 77 2 }
+ 78 1 if (GPIO == GPIO_P4)
+ 79 1 {
+ 80 2 if (GPIOx->Mode == GPIO_PullUp)
+ 81 2 P4M1 &= ~GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // ˫
+ 82 2 if (GPIOx->Mode == GPIO_HighZ)
+ 83 2 P4M1 |= GPIOx->Pin, P4M0 &= ~GPIOx->Pin; //
+ 84 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 85 2 P4M1 |= GPIOx->Pin, P4M0 |= GPIOx->Pin; // ©
+ 86 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 87 2 P4M1 &= ~GPIOx->Pin, P4M0 |= GPIOx->Pin; //
+ 88 2 }
+ 89 1 if (GPIO == GPIO_P5)
+ 90 1 {
+ 91 2 if (GPIOx->Mode == GPIO_PullUp)
+ 92 2 P5M1 &= ~GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // ˫
+ 93 2 if (GPIOx->Mode == GPIO_HighZ)
+ 94 2 P5M1 |= GPIOx->Pin, P5M0 &= ~GPIOx->Pin; //
+ 95 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 96 2 P5M1 |= GPIOx->Pin, P5M0 |= GPIOx->Pin; // ©
+ 97 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 98 2 P5M1 &= ~GPIOx->Pin, P5M0 |= GPIOx->Pin; //
+ 99 2 }
+ 100 1 if (GPIO == GPIO_P6)
+ 101 1 {
+ 102 2 if (GPIOx->Mode == GPIO_PullUp)
+ 103 2 P6M1 &= ~GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // ˫
+ 104 2 if (GPIOx->Mode == GPIO_HighZ)
+ 105 2 P6M1 |= GPIOx->Pin, P6M0 &= ~GPIOx->Pin; //
+ 106 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 107 2 P6M1 |= GPIOx->Pin, P6M0 |= GPIOx->Pin; // ©
+ 108 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 109 2 P6M1 &= ~GPIOx->Pin, P6M0 |= GPIOx->Pin; //
+ 110 2 }
+ 111 1 if (GPIO == GPIO_P7)
+ 112 1 {
+ 113 2 if (GPIOx->Mode == GPIO_PullUp)
+ 114 2 P7M1 &= ~GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // ˫
+ 115 2 if (GPIOx->Mode == GPIO_HighZ)
+ 116 2 P7M1 |= GPIOx->Pin, P7M0 &= ~GPIOx->Pin; //
+ C51 COMPILER V9.60.0.0 GPIO 04/10/2023 15:47:03 PAGE 3
+
+ 117 2 if (GPIOx->Mode == GPIO_OUT_OD)
+ 118 2 P7M1 |= GPIOx->Pin, P7M0 |= GPIOx->Pin; // ©
+ 119 2 if (GPIOx->Mode == GPIO_OUT_PP)
+ 120 2 P7M1 &= ~GPIOx->Pin, P7M0 |= GPIOx->Pin; //
+ 121 2 }
+ 122 1 return 0; // ɹ
+ 123 1 }
+ 124 void GPIO_config(void)
+ 125 {
+ 126 1 GPIO_InitTypeDef GPIO_InitStructure; // ṹ
+ 127 1
+ 128 1 GPIO_InitStructure.Pin = GPIO_Pin_2; // ָҪʼIO, GPIO_Pin_0 ~ GPIO_
+ -Pin_7,
+ 129 1 GPIO_InitStructure.Mode = GPIO_PullUp; // ָIOʽ,GPIO_PullUp,G
+ -PIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP
+ 130 1 GPIO_Inilize(GPIO_P3, &GPIO_InitStructure); // ʼ
+ 131 1 GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2; // ָҪʼIO, GPIO_Pin_0 ~ GPIO_
+ -Pin_7,
+ 132 1 GPIO_InitStructure.Mode = GPIO_OUT_PP; // ָIOʽ,GPIO_PullUp,G
+ -PIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP
+ 133 1 GPIO_Inilize(GPIO_P1, &GPIO_InitStructure); // ʼ
+ 134 1 power1_gpio = 0;
+ 135 1 power2_gpio = 0;
+ 136 1 power3_gpio = 0;
+ 137 1 }
+
+
+MODULE INFORMATION: STATIC OVERLAYABLE
+ CODE SIZE = 665 ----
+ CONSTANT SIZE = ---- ----
+ XDATA SIZE = ---- ----
+ PDATA SIZE = ---- ----
+ DATA SIZE = ---- 2
+ IDATA SIZE = ---- ----
+ BIT SIZE = ---- ----
+END OF MODULE INFORMATION.
+
+
+C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
diff --git a/Listings/STARTUP.lst b/Listings/STARTUP.lst
new file mode 100644
index 0000000..d72e3cc
--- /dev/null
+++ b/Listings/STARTUP.lst
@@ -0,0 +1,253 @@
+A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 1
+
+
+MACRO ASSEMBLER A51 V8.2.7.0
+OBJECT MODULE PLACED IN .\Objects\STARTUP.obj
+ASSEMBLER INVOKED BY: d:\Keil_v5\C51\BIN\A51.EXE STARTUP.A51 SET(SMALL) DEBUG PRINT(.\Listings\STARTUP.lst) OBJECT(.\Obj
+ ects\STARTUP.obj) EP
+
+LOC OBJ LINE SOURCE
+
+ 1 $nomod51
+ 2 ;------------------------------------------------------------------------------
+ 3 ; This file is part of the C51 Compiler package
+ 4 ; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
+ 5 ; Version 8.01
+ 6 ;
+ 7 ; *** <<< Use Configuration Wizard in Context Menu >>> ***
+ 8 ;------------------------------------------------------------------------------
+ 9 ; STARTUP.A51: This code is executed after processor reset.
+ 10 ;
+ 11 ; To translate this file use A51 with the following invocation:
+ 12 ;
+ 13 ; A51 STARTUP.A51
+ 14 ;
+ 15 ; To link the modified STARTUP.OBJ file to your application use the following
+ 16 ; Lx51 invocation:
+ 17 ;
+ 18 ; Lx51 your object file list, STARTUP.OBJ controls
+ 19 ;
+ 20 ;------------------------------------------------------------------------------
+ 21 ;
+ 22 ; User-defined Power-On Initialization of Memory
+ 23 ;
+ 24 ; With the following EQU statements the initialization of memory
+ 25 ; at processor reset can be defined:
+ 26 ;
+ 27 ; IDATALEN: IDATA memory size <0x0-0x100>
+ 28 ; Note: The absolute start-address of IDATA memory is always 0
+ 29 ; The IDATA space overlaps physically the DATA and BIT areas.
+ 0080 30 IDATALEN EQU 80H
+ 31 ;
+ 32 ; XDATASTART: XDATA memory start address <0x0-0xFFFF>
+ 33 ; The absolute start address of XDATA memory
+ 0000 34 XDATASTART EQU 0
+ 35 ;
+ 36 ; XDATALEN: XDATA memory size <0x0-0xFFFF>
+ 37 ; The length of XDATA memory in bytes.
+ 0000 38 XDATALEN EQU 0
+ 39 ;
+ 40 ; PDATASTART: PDATA memory start address <0x0-0xFFFF>
+ 41 ; The absolute start address of PDATA memory
+ 0000 42 PDATASTART EQU 0H
+ 43 ;
+ 44 ; PDATALEN: PDATA memory size <0x0-0xFF>
+ 45 ; The length of PDATA memory in bytes.
+ 0000 46 PDATALEN EQU 0H
+ 47 ;
+ 48 ;
+ 49 ;------------------------------------------------------------------------------
+ 50 ;
+ 51 ; Reentrant Stack Initialization
+ 52 ;
+ 53 ; The following EQU statements define the stack pointer for reentrant
+ 54 ; functions and initialized it:
+ 55 ;
+ 56 ; Stack Space for reentrant functions in the SMALL model.
+ 57 ; IBPSTACK: Enable SMALL model reentrant stack
+ A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 2
+
+ 58 ; Stack space for reentrant functions in the SMALL model.
+ 0000 59 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
+ 60 ; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
+ 61 ; Set the top of the stack to the highest location.
+ 0100 62 IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
+ 63 ;
+ 64 ;
+ 65 ; Stack Space for reentrant functions in the LARGE model.
+ 66 ; XBPSTACK: Enable LARGE model reentrant stack
+ 67 ; Stack space for reentrant functions in the LARGE model.
+ 0000 68 XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
+ 69 ; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
+ 70 ; Set the top of the stack to the highest location.
+ 0000 71 XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
+ 72 ;
+ 73 ;
+ 74 ; Stack Space for reentrant functions in the COMPACT model.
+ 75 ; PBPSTACK: Enable COMPACT model reentrant stack
+ 76 ; Stack space for reentrant functions in the COMPACT model.
+ 0000 77 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
+ 78 ;
+ 79 ; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
+ 80 ; Set the top of the stack to the highest location.
+ 0100 81 PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
+ 82 ;
+ 83 ;
+ 84 ;------------------------------------------------------------------------------
+ 85 ;
+ 86 ; Memory Page for Using the Compact Model with 64 KByte xdata RAM
+ 87 ; Compact Model Page Definition
+ 88 ;
+ 89 ; Define the XDATA page used for PDATA variables.
+ 90 ; PPAGE must conform with the PPAGE set in the linker invocation.
+ 91 ;
+ 92 ; Enable pdata memory page initalization
+ 0000 93 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
+ 94 ;
+ 95 ; PPAGE number <0x0-0xFF>
+ 96 ; uppermost 256-byte address of the page used for PDATA variables.
+ 0000 97 PPAGE EQU 0
+ 98 ;
+ 99 ; SFR address which supplies uppermost address byte <0x0-0xFF>
+ 100 ; most 8051 variants use P2 as uppermost address byte
+ 00A0 101 PPAGE_SFR DATA 0A0H
+ 102 ;
+ 103 ;
+ 104 ;------------------------------------------------------------------------------
+ 105
+ 106 ; Standard SFR Symbols
+ 00E0 107 ACC DATA 0E0H
+ 00F0 108 B DATA 0F0H
+ 0081 109 SP DATA 81H
+ 0082 110 DPL DATA 82H
+ 0083 111 DPH DATA 83H
+ 112
+ 113 NAME ?C_STARTUP
+ 114
+ 115
+ 116 ?C_C51STARTUP SEGMENT CODE
+ 117 ?STACK SEGMENT IDATA
+ 118
+---- 119 RSEG ?STACK
+0000 120 DS 1
+ 121
+ 122 EXTRN CODE (?C_START)
+ 123 PUBLIC ?C_STARTUP
+ A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 3
+
+ 124
+---- 125 CSEG AT 0
+0000 020000 F 126 ?C_STARTUP: LJMP STARTUP1
+ 127
+---- 128 RSEG ?C_C51STARTUP
+ 129
+0000 130 STARTUP1:
+ 131
+ 132 IF IDATALEN <> 0
+0000 787F 133 MOV R0,#IDATALEN - 1
+0002 E4 134 CLR A
+0003 F6 135 IDATALOOP: MOV @R0,A
+0004 D8FD 136 DJNZ R0,IDATALOOP
+ 137 ENDIF
+ 138
+ 139 IF XDATALEN <> 0
+ MOV DPTR,#XDATASTART
+ MOV R7,#LOW (XDATALEN)
+ IF (LOW (XDATALEN)) <> 0
+ MOV R6,#(HIGH (XDATALEN)) +1
+ ELSE
+ MOV R6,#HIGH (XDATALEN)
+ ENDIF
+ CLR A
+ XDATALOOP: MOVX @DPTR,A
+ INC DPTR
+ DJNZ R7,XDATALOOP
+ DJNZ R6,XDATALOOP
+ ENDIF
+ 153
+ 154 IF PPAGEENABLE <> 0
+ MOV PPAGE_SFR,#PPAGE
+ ENDIF
+ 157
+ 158 IF PDATALEN <> 0
+ MOV R0,#LOW (PDATASTART)
+ MOV R7,#LOW (PDATALEN)
+ CLR A
+ PDATALOOP: MOVX @R0,A
+ INC R0
+ DJNZ R7,PDATALOOP
+ ENDIF
+ 166
+ 167 IF IBPSTACK <> 0
+ EXTRN DATA (?C_IBP)
+
+ MOV ?C_IBP,#LOW IBPSTACKTOP
+ ENDIF
+ 172
+ 173 IF XBPSTACK <> 0
+ EXTRN DATA (?C_XBP)
+
+ MOV ?C_XBP,#HIGH XBPSTACKTOP
+ MOV ?C_XBP+1,#LOW XBPSTACKTOP
+ ENDIF
+ 179
+ 180 IF PBPSTACK <> 0
+ EXTRN DATA (?C_PBP)
+ MOV ?C_PBP,#LOW PBPSTACKTOP
+ ENDIF
+ 184
+0006 758100 F 185 MOV SP,#?STACK-1
+ 186
+ 187 ; This code is required if you use L51_BANK.A51 with Banking Mode 4
+ 188 ; Code Banking
+ 189 ; Select Bank 0 for L51_BANK.A51 Mode 4
+ A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 4
+
+ 190
+
+
+
+
+ 195 ;
+0009 020000 F 196 LJMP ?C_START
+ 197
+ 198 END
+ A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 5
+
+SYMBOL TABLE LISTING
+------ ----- -------
+
+
+N A M E T Y P E V A L U E ATTRIBUTES
+
+?C_C51STARTUP. . . C SEG 000CH REL=UNIT
+?C_START . . . . . C ADDR ----- EXT
+?C_STARTUP . . . . C ADDR 0000H A
+?STACK . . . . . . I SEG 0001H REL=UNIT
+ACC. . . . . . . . D ADDR 00E0H A
+B. . . . . . . . . D ADDR 00F0H A
+DPH. . . . . . . . D ADDR 0083H A
+DPL. . . . . . . . D ADDR 0082H A
+IBPSTACK . . . . . N NUMB 0000H A
+IBPSTACKTOP. . . . N NUMB 0100H A
+IDATALEN . . . . . N NUMB 0080H A
+IDATALOOP. . . . . C ADDR 0003H R SEG=?C_C51STARTUP
+PBPSTACK . . . . . N NUMB 0000H A
+PBPSTACKTOP. . . . N NUMB 0100H A
+PDATALEN . . . . . N NUMB 0000H A
+PDATASTART . . . . N NUMB 0000H A
+PPAGE. . . . . . . N NUMB 0000H A
+PPAGEENABLE. . . . N NUMB 0000H A
+PPAGE_SFR. . . . . D ADDR 00A0H A
+SP . . . . . . . . D ADDR 0081H A
+STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP
+XBPSTACK . . . . . N NUMB 0000H A
+XBPSTACKTOP. . . . N NUMB 0000H A
+XDATALEN . . . . . N NUMB 0000H A
+XDATASTART . . . . N NUMB 0000H A
+
+
+REGISTER BANK(S) USED: 0
+
+
+ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)
diff --git a/Listings/kill_control.m51 b/Listings/kill_control.m51
new file mode 100644
index 0000000..22471f6
--- /dev/null
+++ b/Listings/kill_control.m51
@@ -0,0 +1,707 @@
+BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 1
+
+
+BL51 BANKED LINKER/LOCATER V6.22.2.0, INVOKED BY:
+D:\KEIL_V5\C51\BIN\BL51.EXE .\Objects\STARTUP.obj, .\Objects\Exti.obj, .\Objects\GPIO.obj, .\Objects\main.obj, .\Objects
+>> \timer.obj TO .\Objects\kill_control PRINT (.\Listings\kill_control.m51) RAMSIZE (256)
+
+
+MEMORY MODEL: SMALL
+
+
+INPUT MODULES INCLUDED:
+ .\Objects\STARTUP.obj (?C_STARTUP)
+ .\Objects\Exti.obj (EXTI)
+ .\Objects\GPIO.obj (GPIO)
+ .\Objects\main.obj (MAIN)
+ .\Objects\timer.obj (TIMER)
+ D:\KEIL_V5\C51\LIB\C51S.LIB (?C_INIT)
+ D:\KEIL_V5\C51\LIB\C51S.LIB (?C?CLDPTR)
+ D:\KEIL_V5\C51\LIB\C51S.LIB (?C?CLDOPTR)
+ D:\KEIL_V5\C51\LIB\C51S.LIB (?C?ILDOPTR)
+
+
+LINK MAP OF MODULE: .\Objects\kill_control (?C_STARTUP)
+
+
+ TYPE BASE LENGTH RELOCATION SEGMENT NAME
+ -----------------------------------------------------
+
+ * * * * * * * D A T A M E M O R Y * * * * * * *
+ REG 0000H 0008H ABSOLUTE "REG BANK 0"
+ DATA 0008H 0008H UNIT _DATA_GROUP_
+ DATA 0010H 0001H UNIT ?DT?TIMER
+ IDATA 0011H 0001H UNIT ?STACK
+
+ * * * * * * * C O D E M E M O R Y * * * * * * *
+ CODE 0000H 0003H ABSOLUTE
+ CODE 0003H 0003H ABSOLUTE
+ CODE 0006H 0004H UNIT ?C_INITSEG
+ CODE 000AH 0001H UNIT ?PR?EXT_INT1?EXTI
+ CODE 000BH 0003H ABSOLUTE
+ CODE 000EH 0001H UNIT ?PR?EXT_INT2?EXTI
+ CODE 000FH 0001H UNIT ?PR?EXT_INT3?EXTI
+ CODE 0010H 0001H UNIT ?PR?EXT_INT4?EXTI
+ CODE 0011H 0001H UNIT ?PR?TIMER1_INT?TIMER
+ CODE 0012H 0001H UNIT ?PR?TIMER2_INT?TIMER
+ CODE 0013H 0003H ABSOLUTE
+ CODE 0016H 0001H UNIT ?PR?TIMER3_INT?TIMER
+ CODE 0017H 0001H UNIT ?PR?TIMER4_INT?TIMER
+ 0018H 0003H *** GAP ***
+ CODE 001BH 0003H ABSOLUTE
+ CODE 001EH 0022H UNIT ?PR?GPIO_CONFIG?GPIO
+ CODE 0040H 0011H UNIT ?PR?EXTI_CONFIG?EXTI
+ 0051H 0002H *** GAP ***
+ CODE 0053H 0003H ABSOLUTE
+ 0056H 0005H *** GAP ***
+ CODE 005BH 0003H ABSOLUTE
+ 005EH 0005H *** GAP ***
+ CODE 0063H 0003H ABSOLUTE
+ CODE 0066H 0017H UNIT ?PR?EXT_INT0?EXTI
+ 007DH 0006H *** GAP ***
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 2
+
+
+ CODE 0083H 0003H ABSOLUTE
+ CODE 0086H 000DH UNIT ?PR?MAIN?MAIN
+ 0093H 0008H *** GAP ***
+ CODE 009BH 0003H ABSOLUTE
+ 009EH 0005H *** GAP ***
+ CODE 00A3H 0003H ABSOLUTE
+ CODE 00A6H 0331H UNIT ?PR?_TIMER_INILIZE?TIMER
+ CODE 03D7H 0277H UNIT ?PR?_GPIO_INILIZE?GPIO
+ CODE 064EH 0128H UNIT ?PR?_EXT_INILIZE?EXTI
+ CODE 0776H 008CH UNIT ?C_C51STARTUP
+ CODE 0802H 007EH UNIT ?C?LIB_CODE
+ CODE 0880H 001EH UNIT ?PR?TIMER_CONFIG?TIMER
+ CODE 089EH 000BH UNIT ?PR?TIMER0_INT?TIMER
+
+
+
+OVERLAY MAP OF MODULE: .\Objects\kill_control (?C_STARTUP)
+
+
+SEGMENT DATA_GROUP
+ +--> CALLED SEGMENT START LENGTH
+------------------------------------------------
+?C_C51STARTUP ----- -----
+ +--> ?PR?MAIN?MAIN
+ +--> ?C_INITSEG
+
+?PR?MAIN?MAIN ----- -----
+ +--> ?PR?GPIO_CONFIG?GPIO
+ +--> ?PR?EXTI_CONFIG?EXTI
+ +--> ?PR?TIMER_CONFIG?TIMER
+
+?PR?GPIO_CONFIG?GPIO 0008H 0002H
+ +--> ?PR?_GPIO_INILIZE?GPIO
+
+?PR?EXTI_CONFIG?EXTI 0008H 0003H
+ +--> ?PR?_EXT_INILIZE?EXTI
+
+?PR?TIMER_CONFIG?TIMER 0008H 0008H
+ +--> ?PR?_TIMER_INILIZE?TIMER
+
+
+
+SYMBOL TABLE OF MODULE: .\Objects\kill_control (?C_STARTUP)
+
+ VALUE TYPE NAME
+ ----------------------------------
+
+ ------- MODULE ?C_STARTUP
+ C:0776H SEGMENT ?C_C51STARTUP
+ I:0011H SEGMENT ?STACK
+ C:0000H PUBLIC ?C_STARTUP
+ D:00E0H SYMBOL ACC
+ D:00F0H SYMBOL B
+ D:0083H SYMBOL DPH
+ D:0082H SYMBOL DPL
+ N:0000H SYMBOL IBPSTACK
+ N:0100H SYMBOL IBPSTACKTOP
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 3
+
+
+ N:0080H SYMBOL IDATALEN
+ C:0779H SYMBOL IDATALOOP
+ N:0000H SYMBOL PBPSTACK
+ N:0100H SYMBOL PBPSTACKTOP
+ N:0000H SYMBOL PDATALEN
+ N:0000H SYMBOL PDATASTART
+ N:0000H SYMBOL PPAGE
+ N:0000H SYMBOL PPAGEENABLE
+ D:00A0H SYMBOL PPAGE_SFR
+ D:0081H SYMBOL SP
+ C:0776H SYMBOL STARTUP1
+ N:0000H SYMBOL XBPSTACK
+ N:0000H SYMBOL XBPSTACKTOP
+ N:0000H SYMBOL XDATALEN
+ N:0000H SYMBOL XDATASTART
+ C:0000H LINE# 126
+ C:0776H LINE# 133
+ C:0778H LINE# 134
+ C:0779H LINE# 135
+ C:077AH LINE# 136
+ C:077CH LINE# 185
+ C:077FH LINE# 196
+ ------- ENDMOD ?C_STARTUP
+
+ ------- MODULE EXTI
+ C:0000H SYMBOL _ICE_DUMMY_
+ D:0080H PUBLIC P0
+ D:0090H PUBLIC P1
+ D:00A0H PUBLIC P2
+ D:00B0H PUBLIC P3
+ D:00C0H PUBLIC P4
+ D:00C8H PUBLIC P5
+ D:00E8H PUBLIC P6
+ D:00F8H PUBLIC P7
+ D:00A8H PUBLIC IE
+ D:00B8H PUBLIC IP
+ D:00D8H PUBLIC CCON
+ C:0066H PUBLIC Ext_INT0
+ C:000AH PUBLIC Ext_INT1
+ C:000EH PUBLIC Ext_INT2
+ B:0090H.0 PUBLIC P10
+ C:000FH PUBLIC Ext_INT3
+ B:0090H.1 PUBLIC P11
+ C:0010H PUBLIC Ext_INT4
+ B:0090H.2 PUBLIC P12
+ D:0098H PUBLIC SCON
+ B:00B0H.2 PUBLIC P32
+ D:0088H PUBLIC TCON
+ B:0088H.1 PUBLIC IE0
+ B:0088H.3 PUBLIC IE1
+ D:00F0H PUBLIC B
+ D:00E0H PUBLIC ACC
+ B:00A8H.0 PUBLIC EX0
+ B:0088H.0 PUBLIC IT0
+ B:00A8H.2 PUBLIC EX1
+ B:0088H.2 PUBLIC IT1
+ B:00B8H.0 PUBLIC PX0
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 4
+
+
+ B:00B8H.2 PUBLIC PX1
+ D:00B7H PUBLIC IPH
+ C:064EH PUBLIC _Ext_Inilize
+ C:0040H PUBLIC Exti_config
+ D:008FH PUBLIC INT_CLKO
+ D:00D0H PUBLIC PSW
+ ------- PROC EXT_INT0
+ C:0066H LINE# 24
+ C:0068H LINE# 26
+ C:006BH LINE# 27
+ C:006BH LINE# 28
+ C:006FH LINE# 29
+ C:006FH LINE# 30
+ C:0071H LINE# 31
+ C:0073H LINE# 32
+ C:0075H LINE# 33
+ C:0075H LINE# 34
+ C:0077H LINE# 36
+ C:0077H LINE# 37
+ C:007AH LINE# 38
+ C:007AH LINE# 39
+ ------- ENDPROC EXT_INT0
+ ------- PROC EXT_INT1
+ C:000AH LINE# 42
+ C:000AH LINE# 44
+ ------- ENDPROC EXT_INT1
+ ------- PROC EXT_INT2
+ C:000EH LINE# 47
+ C:000EH LINE# 49
+ ------- ENDPROC EXT_INT2
+ ------- PROC EXT_INT3
+ C:000FH LINE# 52
+ C:000FH LINE# 54
+ ------- ENDPROC EXT_INT3
+ ------- PROC EXT_INT4
+ C:0010H LINE# 57
+ C:0010H LINE# 59
+ ------- ENDPROC EXT_INT4
+ ------- PROC _EXT_INILIZE
+ D:0007H SYMBOL EXT
+ D:0001H SYMBOL INTx
+ C:064EH LINE# 68
+ C:064EH LINE# 69
+ C:064EH LINE# 70
+ C:0658H LINE# 71
+ C:065BH LINE# 73
+ C:065EH LINE# 74
+ C:065EH LINE# 75
+ C:0660H LINE# 76
+ C:066AH LINE# 77
+ C:066EH LINE# 79
+ C:0670H LINE# 80
+ C:0680H LINE# 81
+ C:0683H LINE# 82
+ C:06AFH LINE# 83
+ C:06B6H LINE# 84
+ C:06BAH LINE# 86
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 5
+
+
+ C:06BCH LINE# 87
+ C:06BFH LINE# 88
+ C:06BFH LINE# 90
+ C:06C4H LINE# 91
+ C:06C4H LINE# 92
+ C:06C6H LINE# 93
+ C:06D0H LINE# 94
+ C:06D4H LINE# 96
+ C:06D6H LINE# 97
+ C:06E6H LINE# 98
+ C:06E9H LINE# 99
+ C:0715H LINE# 100
+ C:071CH LINE# 101
+ C:0720H LINE# 103
+ C:0722H LINE# 104
+ C:0725H LINE# 105
+ C:0725H LINE# 107
+ C:072AH LINE# 108
+ C:072AH LINE# 109
+ C:0734H LINE# 110
+ C:0739H LINE# 112
+ C:073CH LINE# 113
+ C:073FH LINE# 114
+ C:073FH LINE# 116
+ C:0744H LINE# 117
+ C:0744H LINE# 118
+ C:074EH LINE# 119
+ C:0753H LINE# 121
+ C:0756H LINE# 122
+ C:0759H LINE# 123
+ C:0759H LINE# 125
+ C:075EH LINE# 126
+ C:075EH LINE# 127
+ C:0768H LINE# 128
+ C:076DH LINE# 130
+ C:0770H LINE# 131
+ C:0773H LINE# 132
+ C:0773H LINE# 133
+ C:0775H LINE# 134
+ ------- ENDPROC _EXT_INILIZE
+ ------- PROC EXTI_CONFIG
+ ------- DO
+ D:0008H SYMBOL Exti_InitStructure
+ ------- ENDDO
+ C:0040H LINE# 135
+ C:0040H LINE# 136
+ C:0040H LINE# 139
+ C:0043H LINE# 140
+ C:0046H LINE# 141
+ C:0048H LINE# 142
+ ------- ENDPROC EXTI_CONFIG
+ ------- ENDMOD EXTI
+
+ ------- MODULE GPIO
+ C:0000H SYMBOL _ICE_DUMMY_
+ D:0093H PUBLIC P0M1
+ D:0092H PUBLIC P1M0
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 6
+
+
+ D:0096H PUBLIC P2M0
+ D:0091H PUBLIC P1M1
+ D:0080H PUBLIC P0
+ D:00B2H PUBLIC P3M0
+ D:0095H PUBLIC P2M1
+ D:0090H PUBLIC P1
+ D:00B4H PUBLIC P4M0
+ D:00B1H PUBLIC P3M1
+ D:00A0H PUBLIC P2
+ D:00CAH PUBLIC P5M0
+ D:00B3H PUBLIC P4M1
+ D:00B0H PUBLIC P3
+ D:00CCH PUBLIC P6M0
+ D:00C9H PUBLIC P5M1
+ D:00C0H PUBLIC P4
+ D:00E2H PUBLIC P7M0
+ D:00CBH PUBLIC P6M1
+ D:00C8H PUBLIC P5
+ D:00E8H PUBLIC P6
+ D:00E1H PUBLIC P7M1
+ D:00F8H PUBLIC P7
+ C:001EH PUBLIC GPIO_config
+ D:00A8H PUBLIC IE
+ D:00B8H PUBLIC IP
+ D:00D8H PUBLIC CCON
+ B:0090H.0 PUBLIC P10
+ B:0090H.1 PUBLIC P11
+ B:0090H.2 PUBLIC P12
+ D:0098H PUBLIC SCON
+ D:0088H PUBLIC TCON
+ D:00F0H PUBLIC B
+ D:00E0H PUBLIC ACC
+ C:03D7H PUBLIC _GPIO_Inilize
+ D:00D0H PUBLIC PSW
+ D:0094H PUBLIC P0M0
+ ------- PROC _GPIO_INILIZE
+ D:0007H SYMBOL GPIO
+ D:0001H SYMBOL GPIOx
+ C:03D7H LINE# 28
+ C:03D7H LINE# 29
+ C:03D7H LINE# 30
+ C:03E1H LINE# 31
+ C:03E4H LINE# 32
+ C:03F1H LINE# 33
+ C:03F4H LINE# 34
+ C:03F7H LINE# 35
+ C:03F7H LINE# 36
+ C:03FAH LINE# 37
+ C:0405H LINE# 38
+ C:040CH LINE# 39
+ C:0417H LINE# 40
+ C:041FH LINE# 41
+ C:0429H LINE# 42
+ C:042EH LINE# 43
+ C:043BH LINE# 44
+ C:043BH LINE# 45
+ C:0440H LINE# 46
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 7
+
+
+ C:0440H LINE# 47
+ C:0446H LINE# 48
+ C:0451H LINE# 49
+ C:0456H LINE# 50
+ C:0461H LINE# 51
+ C:0468H LINE# 52
+ C:0472H LINE# 53
+ C:0479H LINE# 54
+ C:0486H LINE# 55
+ C:0486H LINE# 56
+ C:048BH LINE# 57
+ C:048BH LINE# 58
+ C:0491H LINE# 59
+ C:049CH LINE# 60
+ C:04A1H LINE# 61
+ C:04ACH LINE# 62
+ C:04B3H LINE# 63
+ C:04BDH LINE# 64
+ C:04C4H LINE# 65
+ C:04D1H LINE# 66
+ C:04D1H LINE# 67
+ C:04D6H LINE# 68
+ C:04D6H LINE# 69
+ C:04DCH LINE# 70
+ C:04E7H LINE# 71
+ C:04ECH LINE# 72
+ C:04F7H LINE# 73
+ C:04FEH LINE# 74
+ C:0508H LINE# 75
+ C:050FH LINE# 76
+ C:051CH LINE# 77
+ C:051CH LINE# 78
+ C:0521H LINE# 79
+ C:0521H LINE# 80
+ C:0527H LINE# 81
+ C:0532H LINE# 82
+ C:0537H LINE# 83
+ C:0542H LINE# 84
+ C:0549H LINE# 85
+ C:0553H LINE# 86
+ C:055AH LINE# 87
+ C:0567H LINE# 88
+ C:0567H LINE# 89
+ C:056CH LINE# 90
+ C:056CH LINE# 91
+ C:0572H LINE# 92
+ C:057DH LINE# 93
+ C:0582H LINE# 94
+ C:058DH LINE# 95
+ C:0594H LINE# 96
+ C:059EH LINE# 97
+ C:05A5H LINE# 98
+ C:05B2H LINE# 99
+ C:05B2H LINE# 100
+ C:05B7H LINE# 101
+ C:05B7H LINE# 102
+ C:05BDH LINE# 103
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 8
+
+
+ C:05C8H LINE# 104
+ C:05CDH LINE# 105
+ C:05D8H LINE# 106
+ C:05DFH LINE# 107
+ C:05E9H LINE# 108
+ C:05F0H LINE# 109
+ C:05FDH LINE# 110
+ C:05FDH LINE# 111
+ C:0602H LINE# 112
+ C:0602H LINE# 113
+ C:060AH LINE# 114
+ C:0615H LINE# 115
+ C:061BH LINE# 116
+ C:0626H LINE# 117
+ C:062DH LINE# 118
+ C:0637H LINE# 119
+ C:063EH LINE# 120
+ C:064BH LINE# 121
+ C:064BH LINE# 122
+ C:064DH LINE# 123
+ ------- ENDPROC _GPIO_INILIZE
+ ------- PROC GPIO_CONFIG
+ ------- DO
+ D:0008H SYMBOL GPIO_InitStructure
+ ------- ENDDO
+ C:001EH LINE# 124
+ C:001EH LINE# 125
+ C:001EH LINE# 128
+ C:0021H LINE# 129
+ C:0024H LINE# 130
+ C:002EH LINE# 131
+ C:0031H LINE# 132
+ C:0034H LINE# 133
+ C:0039H LINE# 134
+ C:003BH LINE# 135
+ C:003DH LINE# 136
+ C:003FH LINE# 137
+ ------- ENDPROC GPIO_CONFIG
+ ------- ENDMOD GPIO
+
+ ------- MODULE MAIN
+ C:0000H SYMBOL _ICE_DUMMY_
+ D:0080H PUBLIC P0
+ D:0090H PUBLIC P1
+ D:00A0H PUBLIC P2
+ D:00B0H PUBLIC P3
+ D:00C0H PUBLIC P4
+ D:00C8H PUBLIC P5
+ B:00A8H.7 PUBLIC EA
+ D:00E8H PUBLIC P6
+ D:00F8H PUBLIC P7
+ D:00A8H PUBLIC IE
+ D:00B8H PUBLIC IP
+ D:00D8H PUBLIC CCON
+ C:0086H PUBLIC main
+ D:0098H PUBLIC SCON
+ D:0088H PUBLIC TCON
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 9
+
+
+ D:00F0H PUBLIC B
+ D:00E0H PUBLIC ACC
+ D:00D0H PUBLIC PSW
+ ------- PROC MAIN
+ C:0086H LINE# 19
+ C:0086H LINE# 20
+ C:0086H LINE# 21
+ C:0089H LINE# 22
+ C:008CH LINE# 23
+ C:008FH LINE# 24
+ C:0091H LINE# 25
+ C:0091H LINE# 26
+ C:0091H LINE# 27
+ ------- ENDPROC MAIN
+ ------- ENDMOD MAIN
+
+ ------- MODULE TIMER
+ C:0000H SYMBOL _ICE_DUMMY_
+ D:0080H PUBLIC P0
+ D:0090H PUBLIC P1
+ C:089EH PUBLIC timer0_int
+ D:00A0H PUBLIC P2
+ C:0011H PUBLIC timer1_int
+ D:00B0H PUBLIC P3
+ C:0012H PUBLIC timer2_int
+ D:00C0H PUBLIC P4
+ C:0016H PUBLIC timer3_int
+ D:00C8H PUBLIC P5
+ C:0017H PUBLIC timer4_int
+ D:00E8H PUBLIC P6
+ D:00F8H PUBLIC P7
+ D:00A8H PUBLIC IE
+ D:00B8H PUBLIC IP
+ D:00D8H PUBLIC CCON
+ D:0098H PUBLIC SCON
+ D:0089H PUBLIC TMOD
+ D:0088H PUBLIC TCON
+ C:00A6H PUBLIC _Timer_Inilize
+ D:0010H PUBLIC KILL_time
+ D:00AFH PUBLIC IE2
+ D:00F0H PUBLIC B
+ D:008EH PUBLIC AUXR
+ D:00E0H PUBLIC ACC
+ B:00A8H.1 PUBLIC ET0
+ B:00A8H.3 PUBLIC ET1
+ D:008CH PUBLIC TH0
+ D:008DH PUBLIC TH1
+ D:00D6H PUBLIC TH2
+ D:00D4H PUBLIC TH3
+ D:00D2H PUBLIC TH4
+ D:008AH PUBLIC TL0
+ D:008BH PUBLIC TL1
+ D:00D7H PUBLIC TL2
+ D:00D5H PUBLIC TL3
+ B:00B8H.1 PUBLIC PT0
+ D:00D3H PUBLIC TL4
+ B:00B8H.3 PUBLIC PT1
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 10
+
+
+ B:0088H.4 PUBLIC TR0
+ B:0088H.6 PUBLIC TR1
+ D:00D1H PUBLIC T4T3M
+ C:0880H PUBLIC Timer_config
+ D:00B7H PUBLIC IPH
+ D:008FH PUBLIC INT_CLKO
+ D:00D0H PUBLIC PSW
+ ------- PROC TIMER0_INT
+ C:089EH LINE# 22
+ C:08A0H LINE# 24
+ C:08A4H LINE# 25
+ C:08A4H LINE# 26
+ C:08A6H LINE# 27
+ C:08A6H LINE# 28
+ ------- ENDPROC TIMER0_INT
+ ------- PROC TIMER1_INT
+ C:0011H LINE# 31
+ C:0011H LINE# 34
+ ------- ENDPROC TIMER1_INT
+ ------- PROC TIMER2_INT
+ C:0012H LINE# 37
+ C:0012H LINE# 40
+ ------- ENDPROC TIMER2_INT
+ ------- PROC TIMER3_INT
+ C:0016H LINE# 43
+ C:0016H LINE# 46
+ ------- ENDPROC TIMER3_INT
+ ------- PROC TIMER4_INT
+ C:0017H LINE# 49
+ C:0017H LINE# 52
+ ------- ENDPROC TIMER4_INT
+ ------- PROC _TIMER_INILIZE
+ D:0005H SYMBOL TIM
+ D:0001H SYMBOL TIMx
+ C:00A6H LINE# 62
+ C:00A8H LINE# 63
+ C:00A8H LINE# 64
+ C:00B5H LINE# 66
+ C:00BBH LINE# 67
+ C:00BBH LINE# 68
+ C:00BDH LINE# 69
+ C:00CBH LINE# 70
+ C:00CDH LINE# 71
+ C:00E0H LINE# 72
+ C:010CH LINE# 74
+ C:011CH LINE# 75
+ C:0123H LINE# 76
+ C:0133H LINE# 77
+ C:013AH LINE# 78
+ C:0145H LINE# 79
+ C:0148H LINE# 80
+ C:0157H LINE# 81
+ C:015AH LINE# 83
+ C:016CH LINE# 84
+ C:0178H LINE# 85
+ C:017BH LINE# 86
+ C:017BH LINE# 88
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 11
+
+
+ C:0183H LINE# 89
+ C:0183H LINE# 90
+ C:0185H LINE# 91
+ C:0193H LINE# 92
+ C:0195H LINE# 93
+ C:01A8H LINE# 94
+ C:01D4H LINE# 95
+ C:01E4H LINE# 96
+ C:01F0H LINE# 97
+ C:0200H LINE# 98
+ C:0207H LINE# 99
+ C:0212H LINE# 100
+ C:0215H LINE# 101
+ C:0224H LINE# 102
+ C:0227H LINE# 104
+ C:0239H LINE# 105
+ C:0245H LINE# 106
+ C:0248H LINE# 107
+ C:0248H LINE# 109
+ C:024DH LINE# 110
+ C:024DH LINE# 111
+ C:0250H LINE# 112
+ C:025FH LINE# 113
+ C:0262H LINE# 114
+ C:0275H LINE# 115
+ C:0280H LINE# 116
+ C:0287H LINE# 117
+ C:0292H LINE# 118
+ C:0295H LINE# 119
+ C:02A4H LINE# 120
+ C:02A7H LINE# 122
+ C:02B9H LINE# 123
+ C:02C6H LINE# 124
+ C:02C9H LINE# 125
+ C:02C9H LINE# 127
+ C:02CEH LINE# 128
+ C:02CEH LINE# 129
+ C:02D1H LINE# 130
+ C:02E0H LINE# 131
+ C:02E3H LINE# 132
+ C:02F6H LINE# 133
+ C:0301H LINE# 134
+ C:0308H LINE# 135
+ C:0313H LINE# 136
+ C:0316H LINE# 137
+ C:0325H LINE# 138
+ C:0328H LINE# 140
+ C:033AH LINE# 141
+ C:0347H LINE# 142
+ C:034AH LINE# 143
+ C:034AH LINE# 145
+ C:0352H LINE# 146
+ C:0352H LINE# 147
+ C:0355H LINE# 148
+ C:0364H LINE# 149
+ C:0367H LINE# 150
+ C:037CH LINE# 151
+ BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 12
+
+
+ C:0385H LINE# 152
+ C:0390H LINE# 153
+ C:039FH LINE# 154
+ C:03A2H LINE# 155
+ C:03B1H LINE# 156
+ C:03B4H LINE# 158
+ C:03C4H LINE# 159
+ C:03D1H LINE# 160
+ C:03D4H LINE# 161
+ C:03D4H LINE# 162
+ C:03D6H LINE# 163
+ ------- ENDPROC _TIMER_INILIZE
+ ------- PROC TIMER_CONFIG
+ ------- DO
+ D:0008H SYMBOL TIM_InitStructure
+ ------- ENDDO
+ C:0880H LINE# 165
+ C:0880H LINE# 166
+ C:0880H LINE# 168
+ C:0883H LINE# 169
+ C:0885H LINE# 170
+ C:0888H LINE# 171
+ C:088AH LINE# 172
+ C:088CH LINE# 173
+ C:0892H LINE# 174
+ C:0895H LINE# 175
+ ------- ENDPROC TIMER_CONFIG
+ ------- ENDMOD TIMER
+
+ ------- MODULE ?C?CLDPTR
+ C:0802H PUBLIC ?C?CLDPTR
+ ------- ENDMOD ?C?CLDPTR
+
+ ------- MODULE ?C?CLDOPTR
+ C:081BH PUBLIC ?C?CLDOPTR
+ ------- ENDMOD ?C?CLDOPTR
+
+ ------- MODULE ?C?ILDOPTR
+ C:0848H PUBLIC ?C?ILDOPTR
+ ------- ENDMOD ?C?ILDOPTR
+
+Program Size: data=18.0 xdata=0 code=2183
+LINK/LOCATE RUN COMPLETE. 0 WARNING(S), 0 ERROR(S)
diff --git a/Listings/main.lst b/Listings/main.lst
new file mode 100644
index 0000000..56be677
--- /dev/null
+++ b/Listings/main.lst
@@ -0,0 +1,52 @@
+C51 COMPILER V9.60.0.0 MAIN 04/10/2023 15:47:03 PAGE 1
+
+
+C51 COMPILER V9.60.0.0, COMPILATION OF MODULE MAIN
+OBJECT MODULE PLACED IN .\Objects\main.obj
+COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\main.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEN
+ -D PRINT(.\Listings\main.lst) TABS(2) OBJECT(.\Objects\main.obj)
+
+line level source
+
+ 1 /*---------------------------------------------------------------------*/
+ 2 /* --- STC MCU Limited ------------------------------------------------*/
+ 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/
+ 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/
+ 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+ 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+ 7 /* --- Web: www.STCMCU.com --------------------------------------------*/
+ 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+ 9 /* --- QQ: 800003751 -------------------------------------------------*/
+ 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */
+ 11 /*---------------------------------------------------------------------*/
+ 12
+ 13 #include "config.h"
+ 14 #include "GPIO.h"
+ 15 #include "Exti.h"
+ 16 #include "timer.h"
+ 17
+ 18 /******************** ***********************/
+ 19 void main(void)
+ 20 {
+ 21 1 GPIO_config();
+ 22 1 Exti_config();
+ 23 1 Timer_config();
+ 24 1 EA = 1;
+ 25 1 while (1)
+ 26 1 {
+ 27 2 }
+ 28 1 }
+
+
+MODULE INFORMATION: STATIC OVERLAYABLE
+ CODE SIZE = 13 ----
+ CONSTANT SIZE = ---- ----
+ XDATA SIZE = ---- ----
+ PDATA SIZE = ---- ----
+ DATA SIZE = ---- ----
+ IDATA SIZE = ---- ----
+ BIT SIZE = ---- ----
+END OF MODULE INFORMATION.
+
+
+C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
diff --git a/Listings/timer.lst b/Listings/timer.lst
new file mode 100644
index 0000000..04fb58e
--- /dev/null
+++ b/Listings/timer.lst
@@ -0,0 +1,210 @@
+C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 1
+
+
+C51 COMPILER V9.60.0.0, COMPILATION OF MODULE TIMER
+OBJECT MODULE PLACED IN .\Objects\timer.obj
+COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\timer.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTE
+ -ND PRINT(.\Listings\timer.lst) TABS(2) OBJECT(.\Objects\timer.obj)
+
+line level source
+
+ 1 /*---------------------------------------------------------------------*/
+ 2 /* --- STC MCU Limited ------------------------------------------------*/
+ 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/
+ 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/
+ 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+ 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+ 7 /* --- Web: www.STCMCU.com --------------------------------------------*/
+ 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+ 9 /* --- QQ: 800003751 -------------------------------------------------*/
+ 10 /* Ҫڳʹô˴,ڳעʹSTCϼ */
+ 11 /*---------------------------------------------------------------------*/
+ 12
+ 13 /************* ˵ **************
+ 14
+ 15 ļΪSTC8ϵеĶʱʼжϳ,ûļԼҪжϳ.
+ 16
+ 17 ******************************************/
+ 18
+ 19 #include "timer.h"
+ 20 u8 KILL_time = 0;
+ 21 /********************* Timer0жϺ************************/
+ 22 void timer0_int (void) interrupt TIMER0_VECTOR
+ 23 {
+ 24 1 if (KILL_time)
+ 25 1 {
+ 26 2 KILL_time--;
+ 27 2 }
+ 28 1 }
+ 29
+ 30 /********************* Timer1жϺ************************/
+ 31 void timer1_int (void) interrupt TIMER1_VECTOR
+ 32 {
+ 33 1
+ 34 1 }
+ 35
+ 36 /********************* Timer2жϺ************************/
+ 37 void timer2_int (void) interrupt TIMER2_VECTOR
+ 38 {
+ 39 1
+ 40 1 }
+ 41
+ 42 /********************* Timer3жϺ************************/
+ 43 void timer3_int (void) interrupt TIMER3_VECTOR
+ 44 {
+ 45 1
+ 46 1 }
+ 47
+ 48 /********************* Timer4жϺ************************/
+ 49 void timer4_int (void) interrupt TIMER4_VECTOR
+ 50 {
+ 51 1
+ 52 1 }
+ 53
+ 54
+ C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 2
+
+ 55 //========================================================================
+ 56 // : u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx)
+ 57 // : ʱʼ.
+ 58 // : TIMx: ṹ,οtimer.hĶ.
+ 59 // : ɹ0, ղ1,2.
+ 60 // 汾: V1.0, 2012-10-22
+ 61 //========================================================================
+ 62 u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx)
+ 63 {
+ 64 1 if(TIM > Timer4) return 1; //ղ
+ 65 1
+ 66 1 if(TIM == Timer0)
+ 67 1 {
+ 68 2 Timer0_Stop(); //ֹͣ
+ 69 2 if(TIMx->TIM_Interrupt == ENABLE) Timer0_InterruptEnable(); //ж
+ 70 2 else Timer0_InterruptDisable(); //ֹж
+ 71 2 if(TIMx->TIM_Priority > Priority_3) return 2; //
+ 72 2 Timer0_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_
+ -3
+ 73 2
+ 74 2 if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //
+ 75 2 TMOD = (TMOD & ~0x03) | TIMx->TIM_Mode; //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ, 3:
+ - 16λԶװ
+ 76 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer0_12T(); //12T
+ 77 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer0_1T(); //1T
+ 78 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer0_AsCounter(); //Ƶ
+ 79 2 else Timer0_AsTimer(); //ʱ
+ 80 2 if(TIMx->TIM_ClkOut == ENABLE) Timer0_CLKO_Enable(); //ʱ
+ 81 2 else Timer0_CLKO_Disable(); //ʱ
+ 82 2
+ 83 2 T0_Load(TIMx->TIM_Value);
+ 84 2 if(TIMx->TIM_Run == ENABLE) Timer0_Run(); //ʼ
+ 85 2 return 0; //ɹ
+ 86 2 }
+ 87 1
+ 88 1 if(TIM == Timer1)
+ 89 1 {
+ 90 2 Timer1_Stop(); //ֹͣ
+ 91 2 if(TIMx->TIM_Interrupt == ENABLE) Timer1_InterruptEnable(); //ж
+ 92 2 else Timer1_InterruptDisable(); //ֹж
+ 93 2 if(TIMx->TIM_Priority > Priority_3) return 2; //
+ 94 2 Timer1_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_
+ -3
+ 95 2 if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //
+ 96 2 TMOD = (TMOD & ~0x30) | (TIMx->TIM_Mode<<4); //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶ
+ -, 3: ֹͣ
+ 97 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer1_12T(); //12T
+ 98 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer1_1T(); //1T
+ 99 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer1_AsCounter(); //Ƶ
+ 100 2 else Timer1_AsTimer(); //ʱ
+ 101 2 if(TIMx->TIM_ClkOut == ENABLE) Timer1_CLKO_Enable(); //ʱ
+ 102 2 else Timer1_CLKO_Disable(); //ʱ
+ 103 2
+ 104 2 T1_Load(TIMx->TIM_Value);
+ 105 2 if(TIMx->TIM_Run == ENABLE) Timer1_Run(); //ʼ
+ 106 2 return 0; //ɹ
+ 107 2 }
+ 108 1
+ 109 1 if(TIM == Timer2) //Timer2,̶Ϊ16λԶװ, жȼ
+ 110 1 {
+ 111 2 Timer2_Stop(); //ֹͣ
+ 112 2 if(TIMx->TIM_Interrupt == ENABLE) Timer2_InterruptEnable(); //ж
+ C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 3
+
+ 113 2 else Timer2_InterruptDisable(); //ֹж
+ 114 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2;
+ 115 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer2_12T(); //12T
+ 116 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer2_1T(); //1T
+ 117 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer2_AsCounter(); //Ƶ
+ 118 2 else Timer2_AsTimer(); //ʱ
+ 119 2 if(TIMx->TIM_ClkOut == ENABLE) Timer2_CLKO_Enable(); //ʱ
+ 120 2 else Timer2_CLKO_Disable(); //ʱ
+ 121 2
+ 122 2 T2_Load(TIMx->TIM_Value);
+ 123 2 if(TIMx->TIM_Run == ENABLE) Timer2_Run(); //ʼ
+ 124 2 return 0; //ɹ
+ 125 2 }
+ 126 1
+ 127 1 if(TIM == Timer3) //Timer3,̶Ϊ16λԶװ, жȼ
+ 128 1 {
+ 129 2 Timer3_Stop(); //ֹͣ
+ 130 2 if(TIMx->TIM_Interrupt == ENABLE) Timer3_InterruptEnable(); //ж
+ 131 2 else Timer3_InterruptDisable(); //ֹж
+ 132 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2;
+ 133 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer3_12T(); //12T
+ 134 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer3_1T(); //1T
+ 135 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer3_AsCounter(); //Ƶ
+ 136 2 else Timer3_AsTimer(); //ʱ
+ 137 2 if(TIMx->TIM_ClkOut == ENABLE) Timer3_CLKO_Enable(); //ʱ
+ 138 2 else Timer3_CLKO_Disable(); //ʱ
+ 139 2
+ 140 2 T3_Load(TIMx->TIM_Value);
+ 141 2 if(TIMx->TIM_Run == ENABLE) Timer3_Run(); //ʼ
+ 142 2 return 0; //ɹ
+ 143 2 }
+ 144 1
+ 145 1 if(TIM == Timer4) //Timer3,̶Ϊ16λԶװ, жȼ
+ 146 1 {
+ 147 2 Timer4_Stop(); //ֹͣ
+ 148 2 if(TIMx->TIM_Interrupt == ENABLE) Timer4_InterruptEnable(); //ж
+ 149 2 else Timer4_InterruptDisable(); //ֹж
+ 150 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2;
+ 151 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer4_12T(); //12T
+ 152 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer4_1T(); //1T
+ 153 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer4_AsCounter(); //Ƶ
+ 154 2 else Timer4_AsTimer(); //ʱ
+ 155 2 if(TIMx->TIM_ClkOut == ENABLE) Timer4_CLKO_Enable(); //ʱ
+ 156 2 else Timer4_CLKO_Disable(); //ʱ
+ 157 2
+ 158 2 T4_Load(TIMx->TIM_Value);
+ 159 2 if(TIMx->TIM_Run == ENABLE) Timer4_Run(); //ʼ
+ 160 2 return 0; //ɹ
+ 161 2 }
+ 162 1 return 2; //
+ 163 1 }
+ 164 /************************ ??????? ****************************/
+ 165 void Timer_config(void)
+ 166 {
+ 167 1 TIM_InitTypeDef TIM_InitStructure;
+ 168 1 TIM_InitStructure.TIM_Mode = TIM_16BitAutoReload;
+ 169 1 TIM_InitStructure.TIM_Priority = Priority_0;
+ 170 1 TIM_InitStructure.TIM_Interrupt = ENABLE;
+ 171 1 TIM_InitStructure.TIM_ClkSource = TIM_CLOCK_1T;
+ 172 1 TIM_InitStructure.TIM_ClkOut = DISABLE;
+ 173 1 TIM_InitStructure.TIM_Value = 65536UL - (MAIN_Fosc / 1000UL);
+ 174 1 TIM_InitStructure.TIM_Run = ENABLE;
+ C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 4
+
+ 175 1 Timer_Inilize(Timer0,&TIM_InitStructure);
+ 176 1 }
+
+
+MODULE INFORMATION: STATIC OVERLAYABLE
+ CODE SIZE = 862 ----
+ CONSTANT SIZE = ---- ----
+ XDATA SIZE = ---- ----
+ PDATA SIZE = ---- ----
+ DATA SIZE = 1 8
+ IDATA SIZE = ---- ----
+ BIT SIZE = ---- ----
+END OF MODULE INFORMATION.
+
+
+C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
diff --git a/Objects/Exti.__i b/Objects/Exti.__i
new file mode 100644
index 0000000..28e691a
--- /dev/null
+++ b/Objects/Exti.__i
@@ -0,0 +1 @@
+"mycode\Exti.c" OPTIMIZE (8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEND PRINT(.\Listings\Exti.lst) TABS (2) OBJECT(.\Objects\Exti.obj)
\ No newline at end of file
diff --git a/Objects/Exti.obj b/Objects/Exti.obj
new file mode 100644
index 0000000..7572ce6
Binary files /dev/null and b/Objects/Exti.obj differ
diff --git a/Objects/GPIO.__i b/Objects/GPIO.__i
new file mode 100644
index 0000000..13dec64
--- /dev/null
+++ b/Objects/GPIO.__i
@@ -0,0 +1 @@
+"mycode\GPIO.c" OPTIMIZE (8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEND PRINT(.\Listings\GPIO.lst) TABS (2) OBJECT(.\Objects\GPIO.obj)
\ No newline at end of file
diff --git a/Objects/GPIO.obj b/Objects/GPIO.obj
new file mode 100644
index 0000000..d203d77
Binary files /dev/null and b/Objects/GPIO.obj differ
diff --git a/Objects/STARTUP.obj b/Objects/STARTUP.obj
new file mode 100644
index 0000000..e0c8321
Binary files /dev/null and b/Objects/STARTUP.obj differ
diff --git a/Objects/kill_control b/Objects/kill_control
new file mode 100644
index 0000000..ddc36b2
Binary files /dev/null and b/Objects/kill_control differ
diff --git a/Objects/kill_control.LIB b/Objects/kill_control.LIB
new file mode 100644
index 0000000..e8a0a17
Binary files /dev/null and b/Objects/kill_control.LIB differ
diff --git a/Objects/kill_control.__b b/Objects/kill_control.__b
new file mode 100644
index 0000000..1c6452e
--- /dev/null
+++ b/Objects/kill_control.__b
@@ -0,0 +1,7 @@
+TRANSFER
+".\Objects\STARTUP.obj",
+".\Objects\Exti.obj",
+".\Objects\GPIO.obj",
+".\Objects\main.obj",
+".\Objects\timer.obj"
+TO ".\Objects\kill_control.LIB"
diff --git a/Objects/kill_control.build_log.htm b/Objects/kill_control.build_log.htm
new file mode 100644
index 0000000..f4fa3cd
--- /dev/null
+++ b/Objects/kill_control.build_log.htm
@@ -0,0 +1,37 @@
+
+
+
+Vision Build Log
+Tool Versions:
+IDE-Version: Vision V5.27.1.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: xx xx, xx, LIC=WH7DL-0DZI4-3A0DP-MA9EC-R17VA-4MPD4
+
+Tool Versions:
+Toolchain: PK51 Prof. Developers Kit Version: 9.60.0.0
+Toolchain Path: d:\Keil_v5\C51\BIN
+C Compiler: C51.exe V9.60.0.0
+Assembler: A51.exe V8.2.7.0
+Linker/Locator: BL51.exe V6.22.2.0
+Library Manager: LIB51.exe V4.30.1.0
+Hex Converter: OH51.exe V2.7.0.0
+CPU DLL: S8051.DLL V3.122.0.0
+Dialog DLL: DP51.DLL V2.67.0.0
+Project:
+d:\Users\User\Documents\peek250kill control\kill_control.uvproj
+Project File Date: 04/10/2023
+
+Output:
+Build target 'Target 1'
+compiling Exti.c...
+compiling GPIO.c...
+compiling main.c...
+compiling timer.c...
+linking...
+Program Size: data=18.0 xdata=0 code=2183
+creating hex file from ".\Objects\kill_control"...
+".\Objects\kill_control" - 0 Error(s), 0 Warning(s).
+Build Time Elapsed: 00:00:00
+
+
+
diff --git a/Objects/kill_control.hex b/Objects/kill_control.hex
new file mode 100644
index 0000000..7e28a31
--- /dev/null
+++ b/Objects/kill_control.hex
@@ -0,0 +1,163 @@
+:030000000207767E
+:0C077600787FE4F6D8FD7581100207BD05
+:0300030002006692
+:10006600C0E030B20CE510700BB290B291B2928043
+:0700760003751032D0E032E7
+:0300130002000ADE
+:01000A0032C3
+:0300530002000E9A
+:01000E0032BF
+:03005B0002000F91
+:01000F0032BE
+:0300830002001068
+:0100100032BD
+:10064E00EFD394047480948040037F0122EF706195
+:10065E00C28990000212081B64017004D2A88002A5
+:10066E00C2A890000112081BFED3940374809480DC
+:10067E0040037F0222EEFD7C00700553B7FEC2B828
+:10068E00ED64014C700553B7FED2B8ED64024C70A8
+:10069E000543B701C2B8ED64034C700543B701D2F0
+:1006AE00B812080264017004D2888002C2887F00EA
+:1006BE0022EF64017061C28B90000212081B64016C
+:1006CE007004D2AA8002C2AA90000112081BFED3A7
+:1006DE0094037480948040037F0222EEFD7C0070B0
+:1006EE000553B7FBC2BAED64014C700553B7FBD28C
+:1006FE00BAED64024C700543B704C2BAED64034C04
+:10070E00700543B704D2BA12080264017004D28A8B
+:10071E008002C28A7F0022EF6402701590000212DE
+:10072E00081B64017005438F108003538FEF7F0009
+:10073E0022EF6403701590000212081B640170050D
+:10074E00438F208003538FDF7F0022EF64047015E8
+:10075E0090000212081B64017005438F4080035302
+:08076E008FBF7F00227F0222F1
+:10004000750A01E4F508F509FB7A007908FF020654
+:010050004E61
+:1003D700EFD394077480948040037F0122120802B0
+:1003E700FED394037480948040037F0222EF70440D
+:1003F700EE700B90000112081BF4529352941208EE
+:10040700026401700B90000112081B4293F452948E
+:10041700120802FE6402700A90000112081B429340
+:100427004294EE6403700D90000112081BFEF45213
+:1004370093EE4294EF64017046120802FE700B902F
+:10044700000112081BF452915292EE6401700B9056
+:10045700000112081B4291F45292120802640270C2
+:100467000A90000112081B4291429212080264038B
+:10047700700D90000112081BFEF45291EE4292EFAC
+:1004870064027046120802FE700B90000112081BEE
+:10049700F452955296EE6401700B90000112081BFE
+:1004A7004295F452961208026402700A90000112F3
+:1004B700081B429542961208026403700D900001D2
+:1004C70012081BFEF45295EE4296EF640370461233
+:1004D7000802FE700B90000112081BF452B152B2D1
+:1004E700EE6401700B90000112081B42B1F452B286
+:1004F7001208026402700A90000112081B42B142FE
+:10050700B21208026403700D90000112081BFEF47A
+:1005170052B1EE42B2EF64047046120802FE700B4D
+:1005270090000112081BF452B352B4EE6401700B31
+:1005370090000112081B42B3F452B412080264027D
+:10054700700A90000112081B42B342B412080264F9
+:1005570003700D90000112081BFEF452B3EE42B473
+:10056700EF64057046120802FE700B900001120836
+:100577001BF452C952CAEE6401700B9000011208B5
+:100587001B42C9F452CA1208026402700A900001A1
+:1005970012081B42C942CA1208026403700D900078
+:1005A7000112081BFEF452C9EE42CAEF64067046F8
+:1005B700120802FE700B90000112081BF452CB5276
+:1005C700CCEE6401700B90000112081B42CBF45271
+:1005D700CC1208026402700A90000112081B42CB79
+:1005E70042CC1208026403700D90000112081BFE32
+:1005F700F452CBEE42CCEF64077049120802FF7E3B
+:1006070000700B90000112081BF452E152E2EF64F4
+:10061700014E700B90000112081B42E1F452E212E6
+:1006270008026402700A90000112081B42E142E2CC
+:100637001208026403700D90000112081BFFF452A8
+:07064700E1EF42E27F002217
+:10001E00750904E4F508FB7A0079087F031203D70B
+:10002E007509077508037F011203D7C290C291C2EA
+:01003E00922F
+:01003F00229E
+:0D00860012001E120040120880D2AF80FE52
+:03000600011000E6
+:03000B0002089E4A
+:0B089E00C0E0E51060021510D0E03251
+:03001B00020011CF
+:0100110032BC
+:0300630002001286
+:0100120032BB
+:03009B000200164A
+:0100160032B7
+:0300A30002001741
+:0100170032B6
+:1000A600AD07EDD394047480948040037F0122ED64
+:1000B600600302017BC28C90000212081B6401706F
+:1000C60004D2A98002C2A990000112081BFED39493
+:1000D600037480948040037F0222EEFF7E00700549
+:1000E60053B7FDC2B9EF64014E700553B7FDD2B9DF
+:1000F600EF64024E700543B702C2B9EF64034E7057
+:100106000543B702D2B9120802FEC3940374809461
+:100116008040037F0222E58954FC4EF58990000356
+:1001260012081BFF7E0064017003538E7FEF4E7032
+:1001360003438E80EF64024E7005438904800353A7
+:1001460089FB90000412081B64017005438F01802F
+:1001560003538FFE900005120848E5F0F58C9000D9
+:1001660005120848F58A90000712081B6401700200
+:10017600D28C7F0022ED64016003020248C28E9099
+:10018600000212081B64017004D2AB8002C2AB905D
+:10019600000112081BFED394037480948040037FF1
+:1001A6000222EEFF7E00700553B7F7C2BBEF640173
+:1001B6004E700553B7F7D2BBEF64024E700543B7D6
+:1001C60008C2BBEF64034E700543B708D2BB1208E2
+:1001D60002FEC394037480948040037F0222EEC41F
+:1001E60054F0FFE58954CF4FF58990000312081BA0
+:1001F600FF7E0064017003538EBFEF4E7003438E83
+:1002060040EF64024E700543894080035389BF90D6
+:10021600000412081B64017005438F028003538F8C
+:10022600FD900005120848E5F0F58D9000051208CE
+:1002360048F58B90000712081B64017002D28E7F6E
+:100246000022ED6402707C538EEF90000212081BB0
+:100256006401700543AF04800353AFFB90000312A3
+:10026600081BFED394027480948040037F0222EE22
+:10027600FF7E0064017003538EFBEF4E7003438EC6
+:1002860004EF64024E7005438E088003538EF79088
+:10029600000412081B64017005438F048003538F0A
+:1002A600FB900005120848E5F0F5D6900005120807
+:1002B60048F5D790000712081B64017003438E109F
+:1002C6007F0022ED6403707C53D1F7900002120880
+:1002D6001B6401700543AF20800353AFDF9000031A
+:1002E60012081BFED394027480948040037F02227E
+:1002F600EEFF7E006401700353D1FDEF4E700343A1
+:10030600D102EF64024E700543D104800353D1FB42
+:1003160090000412081B6401700543D10180035349
+:10032600D1FE900005120848E5F0F5D490000512BC
+:100336000848F5D590000712081B6401700343D1E5
+:10034600087F0022ED640460030203D453D17F903A
+:10035600000212081B6401700543AF40800353AFCF
+:10036600BF90000312081BFD7C00D3940274809496
+:100376008040037F0222ED64014C700353D1DF906D
+:10038600000312081B700343D12090000312081BC0
+:100396006402700543D140800353D1BF900004121C
+:1003A600081B6401700543D110800353D1EF900000
+:1003B60005120848FDACF0ECF5D2AF058FD39000DE
+:1003C6000712081B6401700343D1807F00227F025D
+:0103D6002204
+:10088000E4F508F509750A01F50BF50C750DD4753D
+:0E0890000ECD750F01FB7A007908FF0200A65D
+:10078200020086E493A3F8E493A34003F68001F207
+:1007920008DFF48029E493A3F85407240CC8C33378
+:1007A200C4540F4420C8834004F456800146F6DF47
+:1007B200E4800B0102040810204080900006E47ED1
+:1007C200019360BCA3FF543F30E509541FFEE4933C
+:1007D200A360010ECF54C025E060A840B8E493A303
+:1007E200FAE493A3F8E493A3C8C582C8CAC583CA2E
+:1007F200F0A3C8C582C8CAC583CADFE9DEE780BEE6
+:0100090000F6
+:10080200BB010689828A83E0225002E722BBFE02F4
+:09081200E32289828A83E4932227
+:10081B00BB010CE58229F582E5833AF583E0225092
+:10082B0006E92582F8E622BBFE06E92582F8E222DC
+:0D083B00E58229F582E5833AF583E49322F6
+:10084800BB0110E58229F582E5833AF583E0F5F0EE
+:10085800A3E0225009E92582F886F008E622BBFECB
+:100868000AE92582F8E2F5F008E222E5832AF58311
+:08087800E993F5F0A3E99322D6
+:00000001FF
diff --git a/Objects/kill_control.lnp b/Objects/kill_control.lnp
new file mode 100644
index 0000000..6310e39
--- /dev/null
+++ b/Objects/kill_control.lnp
@@ -0,0 +1,7 @@
+".\Objects\STARTUP.obj",
+".\Objects\Exti.obj",
+".\Objects\GPIO.obj",
+".\Objects\main.obj",
+".\Objects\timer.obj"
+TO ".\Objects\kill_control"
+PRINT(".\Listings\kill_control.m51") RAMSIZE(256)
diff --git a/Objects/main.__i b/Objects/main.__i
new file mode 100644
index 0000000..442891a
--- /dev/null
+++ b/Objects/main.__i
@@ -0,0 +1 @@
+"mycode\main.c" OPTIMIZE (8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEND PRINT(.\Listings\main.lst) TABS (2) OBJECT(.\Objects\main.obj)
\ No newline at end of file
diff --git a/Objects/main.obj b/Objects/main.obj
new file mode 100644
index 0000000..5f0af08
Binary files /dev/null and b/Objects/main.obj differ
diff --git a/Objects/timer.__i b/Objects/timer.__i
new file mode 100644
index 0000000..695df70
--- /dev/null
+++ b/Objects/timer.__i
@@ -0,0 +1 @@
+"mycode\timer.c" OPTIMIZE (8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEND PRINT(.\Listings\timer.lst) TABS (2) OBJECT(.\Objects\timer.obj)
\ No newline at end of file
diff --git a/Objects/timer.obj b/Objects/timer.obj
new file mode 100644
index 0000000..f51be80
Binary files /dev/null and b/Objects/timer.obj differ
diff --git a/STARTUP.A51 b/STARTUP.A51
new file mode 100644
index 0000000..ec99b9e
--- /dev/null
+++ b/STARTUP.A51
@@ -0,0 +1,198 @@
+$NOMOD51
+;------------------------------------------------------------------------------
+; This file is part of the C51 Compiler package
+; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
+; Version 8.01
+;
+; *** <<< Use Configuration Wizard in Context Menu >>> ***
+;------------------------------------------------------------------------------
+; STARTUP.A51: This code is executed after processor reset.
+;
+; To translate this file use A51 with the following invocation:
+;
+; A51 STARTUP.A51
+;
+; To link the modified STARTUP.OBJ file to your application use the following
+; Lx51 invocation:
+;
+; Lx51 your object file list, STARTUP.OBJ controls
+;
+;------------------------------------------------------------------------------
+;
+; User-defined Power-On Initialization of Memory
+;
+; With the following EQU statements the initialization of memory
+; at processor reset can be defined:
+;
+; IDATALEN: IDATA memory size <0x0-0x100>
+; Note: The absolute start-address of IDATA memory is always 0
+; The IDATA space overlaps physically the DATA and BIT areas.
+IDATALEN EQU 80H
+;
+; XDATASTART: XDATA memory start address <0x0-0xFFFF>
+; The absolute start address of XDATA memory
+XDATASTART EQU 0
+;
+; XDATALEN: XDATA memory size <0x0-0xFFFF>
+; The length of XDATA memory in bytes.
+XDATALEN EQU 0
+;
+; PDATASTART: PDATA memory start address <0x0-0xFFFF>
+; The absolute start address of PDATA memory
+PDATASTART EQU 0H
+;
+; PDATALEN: PDATA memory size <0x0-0xFF>
+; The length of PDATA memory in bytes.
+PDATALEN EQU 0H
+;
+;
+;------------------------------------------------------------------------------
+;
+; Reentrant Stack Initialization
+;
+; The following EQU statements define the stack pointer for reentrant
+; functions and initialized it:
+;
+; Stack Space for reentrant functions in the SMALL model.
+; IBPSTACK: Enable SMALL model reentrant stack
+; Stack space for reentrant functions in the SMALL model.
+IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
+; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
+; Set the top of the stack to the highest location.
+IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
+;
+;
+; Stack Space for reentrant functions in the LARGE model.
+; XBPSTACK: Enable LARGE model reentrant stack
+; Stack space for reentrant functions in the LARGE model.
+XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
+; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
+; Set the top of the stack to the highest location.
+XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
+;
+;
+; Stack Space for reentrant functions in the COMPACT model.
+; PBPSTACK: Enable COMPACT model reentrant stack
+; Stack space for reentrant functions in the COMPACT model.
+PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
+;
+; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
+; Set the top of the stack to the highest location.
+PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
+;
+;
+;------------------------------------------------------------------------------
+;
+; Memory Page for Using the Compact Model with 64 KByte xdata RAM
+; Compact Model Page Definition
+;
+; Define the XDATA page used for PDATA variables.
+; PPAGE must conform with the PPAGE set in the linker invocation.
+;
+; Enable pdata memory page initalization
+PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
+;
+; PPAGE number <0x0-0xFF>
+; uppermost 256-byte address of the page used for PDATA variables.
+PPAGE EQU 0
+;
+; SFR address which supplies uppermost address byte <0x0-0xFF>
+; most 8051 variants use P2 as uppermost address byte
+PPAGE_SFR DATA 0A0H
+;
+;
+;------------------------------------------------------------------------------
+
+; Standard SFR Symbols
+ACC DATA 0E0H
+B DATA 0F0H
+SP DATA 81H
+DPL DATA 82H
+DPH DATA 83H
+
+ NAME ?C_STARTUP
+
+
+?C_C51STARTUP SEGMENT CODE
+?STACK SEGMENT IDATA
+
+ RSEG ?STACK
+ DS 1
+
+ EXTRN CODE (?C_START)
+ PUBLIC ?C_STARTUP
+
+ CSEG AT 0
+?C_STARTUP: LJMP STARTUP1
+
+ RSEG ?C_C51STARTUP
+
+STARTUP1:
+
+IF IDATALEN <> 0
+ MOV R0,#IDATALEN - 1
+ CLR A
+IDATALOOP: MOV @R0,A
+ DJNZ R0,IDATALOOP
+ENDIF
+
+IF XDATALEN <> 0
+ MOV DPTR,#XDATASTART
+ MOV R7,#LOW (XDATALEN)
+ IF (LOW (XDATALEN)) <> 0
+ MOV R6,#(HIGH (XDATALEN)) +1
+ ELSE
+ MOV R6,#HIGH (XDATALEN)
+ ENDIF
+ CLR A
+XDATALOOP: MOVX @DPTR,A
+ INC DPTR
+ DJNZ R7,XDATALOOP
+ DJNZ R6,XDATALOOP
+ENDIF
+
+IF PPAGEENABLE <> 0
+ MOV PPAGE_SFR,#PPAGE
+ENDIF
+
+IF PDATALEN <> 0
+ MOV R0,#LOW (PDATASTART)
+ MOV R7,#LOW (PDATALEN)
+ CLR A
+PDATALOOP: MOVX @R0,A
+ INC R0
+ DJNZ R7,PDATALOOP
+ENDIF
+
+IF IBPSTACK <> 0
+EXTRN DATA (?C_IBP)
+
+ MOV ?C_IBP,#LOW IBPSTACKTOP
+ENDIF
+
+IF XBPSTACK <> 0
+EXTRN DATA (?C_XBP)
+
+ MOV ?C_XBP,#HIGH XBPSTACKTOP
+ MOV ?C_XBP+1,#LOW XBPSTACKTOP
+ENDIF
+
+IF PBPSTACK <> 0
+EXTRN DATA (?C_PBP)
+ MOV ?C_PBP,#LOW PBPSTACKTOP
+ENDIF
+
+ MOV SP,#?STACK-1
+
+; This code is required if you use L51_BANK.A51 with Banking Mode 4
+; Code Banking
+; Select Bank 0 for L51_BANK.A51 Mode 4
+#if 0
+; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4.
+EXTRN CODE (?B_SWITCH0)
+ CALL ?B_SWITCH0 ; init bank mechanism to code bank 0
+#endif
+;
+ LJMP ?C_START
+
+ END
diff --git a/kill_control.uvgui.User b/kill_control.uvgui.User
new file mode 100644
index 0000000..28b821c
--- /dev/null
+++ b/kill_control.uvgui.User
@@ -0,0 +1,1914 @@
+
+
+
+ -6.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+
+
+
+
+
+
+ 38003
+ Registers
+ 254 56
+
+
+ 346
+ Code Coverage
+ 1410 160
+
+
+ 204
+ Performance Analyzer
+ 1570
+
+
+
+
+
+ 35141
+ Event Statistics
+
+ 200 50 700
+
+
+ 1506
+ Symbols
+
+ 143 143 143
+
+
+ 1936
+ Watch 1
+
+ 200 133 133
+
+
+ 1937
+ Watch 2
+
+ 200 133 133
+
+
+ 1935
+ Call Stack + Locals
+
+ 200 133 133
+
+
+ 2506
+ Trace Data
+
+ 75 135 130 95 70 230 200 150
+
+
+ 466
+ Source Browser
+ 500
+ 166
+
+
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ -1
+
+
+
+
+
+
+ 44
+ 0
+ 1
+
+ -1
+ -1
+
+
+ -1
+ -1
+
+
+ 60
+ 770
+ 2513
+ 1107
+
+
+
+ 0
+
+ 575
+ 01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000005000000030000000100000039443A5C55736572735C557365725C446F63756D656E74735C7065656B3235306B696C6C20636F6E74726F6C5C6D79636F64655C6D61696E2E6300000000066D61696E2E6300000000C5D4F200FFFFFFFF39443A5C55736572735C557365725C446F63756D656E74735C7065656B3235306B696C6C20636F6E74726F6C5C6D79636F64655C4750494F2E6300000000064750494F2E6300000000FFDC7800FFFFFFFF38443A5C55736572735C557365725C446F63756D656E74735C7065656B3235306B696C6C20636F6E74726F6C5C6D79696E635C4750494F2E6800000000064750494F2E6800000000BECEA100FFFFFFFF39443A5C55736572735C557365725C446F63756D656E74735C7065656B3235306B696C6C20636F6E74726F6C5C6D79636F64655C457874692E630000000006457874692E6300000000F0A0A100FFFFFFFF38443A5C55736572735C557365725C446F63756D656E74735C7065656B3235306B696C6C20636F6E74726F6C5C6D79696E635C457874692E680000000006457874692E6800000000BCA8E100FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD5000100000000000000020000004E040000AA000000C90900009E020000
+
+
+
+ 0
+ Build
+
+ -1
+ -1
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 440100004F0000007007000013010000
+
+
+ 16
+ 4E040000AA0000007A0A00006E010000
+
+
+
+ 1005
+ 1005
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000660000003D0100002A020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 109
+ 109
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000660000003D0100002A020000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 1465
+ 1465
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1466
+ 1466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1467
+ 1467
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1468
+ 1468
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1506
+ 1506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 16384
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 1913
+ 1913
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1935
+ 1935
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 1936
+ 1936
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 1937
+ 1937
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 1939
+ 1939
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1940
+ 1940
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1941
+ 1941
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 1942
+ 1942
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 195
+ 195
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000660000003D0100002A020000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 196
+ 196
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000660000003D0100002A020000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 197
+ 197
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 000000005B020000BF060000DD030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 198
+ 198
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 32768
+ 0
+
+ 16
+ 00000000ED02000070070000C5030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 199
+ 199
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000005E020000BC060000C4030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 203
+ 203
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 8192
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 204
+ 204
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 221
+ 221
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000000000000000000000000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 2506
+ 2506
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 2507
+ 2507
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 343
+ 343
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 346
+ 346
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 35141
+ 35141
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35824
+ 35824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 35885
+ 35885
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35886
+ 35886
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35887
+ 35887
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35888
+ 35888
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35889
+ 35889
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35890
+ 35890
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35891
+ 35891
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35892
+ 35892
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35893
+ 35893
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35894
+ 35894
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35895
+ 35895
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35896
+ 35896
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35897
+ 35897
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35898
+ 35898
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35899
+ 35899
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35900
+ 35900
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35901
+ 35901
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35902
+ 35902
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35903
+ 35903
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35904
+ 35904
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 35905
+ 35905
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 38003
+ 38003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000660000003D0100002A020000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 38007
+ 38007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000005E020000BC060000C4030000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 436
+ 436
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000005E020000BC060000C4030000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 437
+ 437
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 440
+ 440
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 463
+ 463
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000005E020000BC060000C4030000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 466
+ 466
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 030000005E020000BC060000C4030000
+
+
+ 16
+ 3C00000053000000B801000067030000
+
+
+
+ 470
+ 470
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 47010000660000006D070000FA000000
+
+
+ 16
+ 3C00000053000000F403000017010000
+
+
+
+ 50000
+ 50000
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50001
+ 50001
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50002
+ 50002
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50003
+ 50003
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50004
+ 50004
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50005
+ 50005
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50006
+ 50006
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50007
+ 50007
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50008
+ 50008
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50009
+ 50009
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50010
+ 50010
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50011
+ 50011
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50012
+ 50012
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50013
+ 50013
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50014
+ 50014
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50015
+ 50015
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50016
+ 50016
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50017
+ 50017
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50018
+ 50018
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 50019
+ 50019
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 33060000660000006D070000E4020000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 59392
+ 59392
+ 1
+ 0
+ 0
+ 0
+ 966
+ 0
+ 8192
+ 0
+
+ 16
+ 0200000000000000D30300001C000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59393
+ 0
+ 1
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 00000000DD030000BF060000F0030000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59399
+ 59399
+ 1
+ 0
+ 0
+ 0
+ 476
+ 0
+ 8192
+ 1
+
+ 16
+ 000000001C000000E701000038000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 59400
+ 59400
+ 0
+ 0
+ 0
+ 0
+ 612
+ 0
+ 8192
+ 2
+
+ 16
+ 00000000380000006F02000054000000
+
+
+ 16
+ 0A0000000A0000006E0000006E000000
+
+
+
+ 824
+ 824
+ 0
+ 0
+ 0
+ 0
+ 32767
+ 0
+ 4096
+ 0
+
+ 16
+ 03000000040300006D070000AC030000
+
+
+ 16
+ 3C000000530000007C01000064010000
+
+
+
+ 3312
+ 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFF44010000130100007007000017010000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E6500200000000000004E040000AA0000007A0A00006E010000440100004F00000070070000130100000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF2C0600004F00000030060000FD020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C30000018000400000000000003A090000AA0000007A0A000058030000300600004F00000070070000FD02000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFF400100004F0000004401000043020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000A030000AA0000004A0400009E020000000000004F00000040010000430200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF00000000E902000070070000ED02000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB090000018000800000000000000A030000480300007A0A00002004000000000000ED02000070070000C503000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFB8030000ED020000BC030000C503000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF0000000043020000BF06000047020000010000000100001004000000010000006DFDFFFF59020000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF01000077940000018000800000010000000A030000A2020000C9090000380400000000000047020000BF060000DD0300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000
+
+
+ 59392
+ File
+
+ 2951
+ 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000004000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000D54494D5F434C4F434B5F457874960000000000000014000D54494D5F434C4F434B5F4578740D54494D5F436C6B536F757263650954494D5F56616C75650A52585F54696D654F75740652585F436E7407425F52585F4F4B0D466C6173685F5265616441727261766F696420466C6173685F5265616441727228756E7369676E656420696E74206675695F416464726573732C756E7369676E65642063686172206675635F4C656E6774682C756E7369676E65642063686172202A667563705F5361766541727229062055415254320555415254320D4D61696E5F466F73635F4B485A1D48414C5F54494D5F506572696F64456C617073656443616C6C6261636B1148414C5F54494D5F49525148616E646C651148414C5F554152545F5472616E736D69741348414C5F554152545F5472616E736D69742829047561727404383030301077733238313253686F7754776F4C6564022D3E012E0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 1423
+ 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000
+
+
+
+ 59399
+ Build
+
+ 976
+ 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000004002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000004004E00000000000000000000000000000000010000000100000001807202000000000400530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 583
+ 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000
+
+
+
+ 59400
+ Debug
+
+ 2373
+ 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000003400000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000
+
+
+ 898
+ 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000
+
+
+
+ 0
+ 3440
+ 1440
+
+
+
+
+
+ 1
+ 0
+
+ 100
+ 3
+
+ .\mycode\main.c
+ 15
+ 1
+ 21
+ 1
+
+ 0
+
+
+ .\mycode\GPIO.c
+ 0
+ 76
+ 100
+ 1
+
+ 0
+
+
+ \Users\User\Documents\peek250kill control\myinc\GPIO.h
+ 0
+ 27
+ 42
+ 1
+
+ 0
+
+
+ .\mycode\Exti.c
+ 20
+ 19
+ 30
+ 1
+
+ 0
+
+
+ .\myinc\Exti.h
+ 17
+ 11
+ 17
+ 1
+
+ 0
+
+
+
+
+
diff --git a/kill_control.uvopt b/kill_control.uvopt
new file mode 100644
index 0000000..77c4d96
--- /dev/null
+++ b/kill_control.uvopt
@@ -0,0 +1,241 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ Target 1
+ 0x0
+ MCS-51
+
+ 35000000
+
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 0
+ 65535
+ 0
+ 0
+ 0
+
+
+ 120
+ 65
+ 8
+ .\Listings\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 255
+
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ -1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0
+
+
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+ Source Group 1
+ 0
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 2
+ 0
+ 0
+ 0
+ .\STARTUP.A51
+ STARTUP.A51
+ 0
+ 0
+
+
+
+
+ mycode
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 2
+ 1
+ 0
+ 0
+ 0
+ .\mycode\Exti.c
+ Exti.c
+ 0
+ 0
+
+
+ 2
+ 3
+ 1
+ 0
+ 0
+ 0
+ .\mycode\GPIO.c
+ GPIO.c
+ 0
+ 0
+
+
+ 2
+ 4
+ 1
+ 0
+ 0
+ 0
+ .\mycode\main.c
+ main.c
+ 0
+ 0
+
+
+ 2
+ 5
+ 1
+ 0
+ 0
+ 0
+ .\mycode\timer.c
+ timer.c
+ 0
+ 0
+
+
+
+
diff --git a/kill_control.uvproj b/kill_control.uvproj
new file mode 100644
index 0000000..8d02049
--- /dev/null
+++ b/kill_control.uvproj
@@ -0,0 +1,415 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Target 1
+ 0x0
+ MCS-51
+ 0
+
+
+ STC8H1K28 Series
+ STC
+ IRAM(0-0xFF) XRAM(0-0x03FF) IROM(0-0x6FF8) CLOCK(35000000) MODP2
+
+ "LIB\STARTUP.A51" ("Standard 8051 Startup Code")
+
+ 63268
+ STC8.H
+
+
+
+
+
+
+
+
+
+
+ 0
+ 0
+
+
+
+ STC\
+ STC\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ kill_control
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\Listings\
+ 0
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+ 65535
+
+
+ S8051.DLL
+
+ DP51.DLL
+ -pDP8051
+ S8051.DLL
+
+ TP51.DLL
+ -p51
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 16
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+
+
+ 0
+ 1
+ 0
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+
+ 0
+ -1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ -1
+
+ 0
+
+
+
+
+
+
+ 0
+
+
+
+ 0
+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0x0
+ 0xffff
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x6ff9
+
+
+ 0
+ 0x0
+ 0x100
+
+
+ 0
+ 0x0
+ 0x400
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+ 0
+ 0
+ 1
+ 0
+ 1
+ 3
+ 8
+ 2
+ 1
+ 1
+ 0
+ 0
+
+
+
+
+ .\myinc
+
+
+
+ 0
+ 1
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 0
+ 0
+ 1
+ 0
+ 2
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Source Group 1
+
+
+ STARTUP.A51
+ 2
+ .\STARTUP.A51
+
+
+
+
+ mycode
+
+
+ Exti.c
+ 1
+ .\mycode\Exti.c
+
+
+ GPIO.c
+ 1
+ .\mycode\GPIO.c
+
+
+ main.c
+ 1
+ .\mycode\main.c
+
+
+ timer.c
+ 1
+ .\mycode\timer.c
+
+
+
+
+
+
+
+
diff --git a/mycode/Exti.c b/mycode/Exti.c
new file mode 100644
index 0000000..2d6fc4b
--- /dev/null
+++ b/mycode/Exti.c
@@ -0,0 +1,143 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* Ҫڳʹô˴,ڳעʹSTCϼ */
+/*---------------------------------------------------------------------*/
+
+/************* ˵ **************
+
+ļΪSTC8ϵежϳʼжϳ,ûļԼҪжϳ.
+
+******************************************/
+
+#include "Exti.h"
+
+/************* ⲿͱ *****************/
+
+/********************* INT0жϺ *************************/
+void Ext_INT0(void) interrupt INT0_VECTOR // жʱѾ־
+{
+ if (kill_gpio)
+ {
+ if (KILL_time == 0)
+ {
+ power1_gpio = !power1_gpio;
+ power2_gpio = !power2_gpio;
+ power3_gpio = !power3_gpio;
+ }
+ }
+ else
+ {
+ KILL_time = 50;
+ }
+}
+
+/********************* INT1жϺ *************************/
+void Ext_INT1(void) interrupt INT1_VECTOR // жʱѾ־
+{
+}
+
+/********************* INT2жϺ *************************/
+void Ext_INT2(void) interrupt INT2_VECTOR //
+{
+}
+
+/********************* INT3жϺ *************************/
+void Ext_INT3(void) interrupt INT3_VECTOR
+{
+}
+
+/********************* INT4жϺ *************************/
+void Ext_INT4(void) interrupt INT4_VECTOR
+{
+}
+
+//========================================================================
+// : u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx)
+// : ⲿжϳʼ.
+// : INTx: ṹ,οExti.hĶ.
+// : ɹ0, ղ1,2.
+// 汾: V1.0, 2012-10-22
+//========================================================================
+u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx)
+{
+ if (EXT > EXT_INT4)
+ return 1; // ղ
+
+ if (EXT == EXT_INT0) // ж0
+ {
+ IE0 = 0; // ж0־λ
+ if (INTx->EXTI_Interrupt == ENABLE)
+ EX0 = 1; // ж
+ else
+ EX0 = 0; // ֹж
+ if (INTx->EXTI_Priority > Priority_3)
+ return 2; //
+ INT0_Priority(INTx->EXTI_Priority); // ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3
+ if (INTx->EXTI_Mode == EXT_MODE_Fall)
+ IT0 = 1; // ½ж
+ else
+ IT0 = 0; // ,½ж
+ return 0; // ɹ
+ }
+
+ if (EXT == EXT_INT1) // ж1
+ {
+ IE1 = 0; // ж1־λ
+ if (INTx->EXTI_Interrupt == ENABLE)
+ EX1 = 1; // ж
+ else
+ EX1 = 0; // ֹж
+ if (INTx->EXTI_Priority > Priority_3)
+ return 2; //
+ INT1_Priority(INTx->EXTI_Priority); // ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3
+ if (INTx->EXTI_Mode == EXT_MODE_Fall)
+ IT1 = 1; // ½ж
+ else
+ IT1 = 0; // ,½ж
+ return 0; // ɹ
+ }
+
+ if (EXT == EXT_INT2) // ж2, ̶Ϊ½صȼж
+ {
+ if (INTx->EXTI_Interrupt == ENABLE)
+ INT_CLKO |= (1 << 4); // ж
+ else
+ INT_CLKO &= ~(1 << 4); // ֹж
+ return 0; // ɹ
+ }
+
+ if (EXT == EXT_INT3) // ж3, ̶Ϊ½صȼж
+ {
+ if (INTx->EXTI_Interrupt == ENABLE)
+ INT_CLKO |= (1 << 5); // ж
+ else
+ INT_CLKO &= ~(1 << 5); // ֹж
+ return 0; // ɹ
+ }
+
+ if (EXT == EXT_INT4) // ж4, ̶Ϊ½صȼж
+ {
+ if (INTx->EXTI_Interrupt == ENABLE)
+ INT_CLKO |= (1 << 6); // ж
+ else
+ INT_CLKO &= ~(1 << 6); // ֹж
+ return 0; // ɹ
+ }
+ return 2; // ʧ
+}
+void Exti_config(void)
+{
+ EXTI_InitTypeDef Exti_InitStructure; // ṹ
+
+ Exti_InitStructure.EXTI_Interrupt = ENABLE; // жʹ, ENABLEDISABLE
+ Exti_InitStructure.EXTI_Mode = EXT_MODE_RiseFall; // жģʽ, EXT_MODE_RiseFall,EXT_MODE_Fall
+ Exti_InitStructure.EXTI_Priority = Priority_0; // ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3
+ Ext_Inilize(EXT_INT0, &Exti_InitStructure); // ʼ
+}
\ No newline at end of file
diff --git a/mycode/GPIO.c b/mycode/GPIO.c
new file mode 100644
index 0000000..974229c
--- /dev/null
+++ b/mycode/GPIO.c
@@ -0,0 +1,137 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* Ҫڳʹô˴,ڳעʹSTCϼ */
+/*---------------------------------------------------------------------*/
+
+/*************** ˵ ****************
+
+ļΪSTC8ϵеĶ˿ڳʼ,ûԲ.
+
+******************************************/
+
+#include "GPIO.h"
+
+//========================================================================
+// : u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx)
+// : ʼIO.
+// : GPIOx: ṹ,οtimer.hĶ.
+// : ɹ0, ղ1,2.
+// 汾: V1.0, 2012-10-22
+//========================================================================
+u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx)
+{
+ if (GPIO > GPIO_P7)
+ return 1; // ղ
+ if (GPIOx->Mode > GPIO_OUT_PP)
+ return 2; //
+ if (GPIO == GPIO_P0)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P0M1 &= ~GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P0M1 |= GPIOx->Pin, P0M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P0M1 |= GPIOx->Pin, P0M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P0M1 &= ~GPIOx->Pin, P0M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P1)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P1M1 &= ~GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P1M1 |= GPIOx->Pin, P1M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P1M1 |= GPIOx->Pin, P1M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P1M1 &= ~GPIOx->Pin, P1M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P2)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P2M1 &= ~GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P2M1 |= GPIOx->Pin, P2M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P2M1 |= GPIOx->Pin, P2M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P2M1 &= ~GPIOx->Pin, P2M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P3)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P3M1 &= ~GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P3M1 |= GPIOx->Pin, P3M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P3M1 |= GPIOx->Pin, P3M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P3M1 &= ~GPIOx->Pin, P3M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P4)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P4M1 &= ~GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P4M1 |= GPIOx->Pin, P4M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P4M1 |= GPIOx->Pin, P4M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P4M1 &= ~GPIOx->Pin, P4M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P5)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P5M1 &= ~GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P5M1 |= GPIOx->Pin, P5M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P5M1 |= GPIOx->Pin, P5M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P5M1 &= ~GPIOx->Pin, P5M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P6)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P6M1 &= ~GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P6M1 |= GPIOx->Pin, P6M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P6M1 |= GPIOx->Pin, P6M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P6M1 &= ~GPIOx->Pin, P6M0 |= GPIOx->Pin; //
+ }
+ if (GPIO == GPIO_P7)
+ {
+ if (GPIOx->Mode == GPIO_PullUp)
+ P7M1 &= ~GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // ˫
+ if (GPIOx->Mode == GPIO_HighZ)
+ P7M1 |= GPIOx->Pin, P7M0 &= ~GPIOx->Pin; //
+ if (GPIOx->Mode == GPIO_OUT_OD)
+ P7M1 |= GPIOx->Pin, P7M0 |= GPIOx->Pin; // ©
+ if (GPIOx->Mode == GPIO_OUT_PP)
+ P7M1 &= ~GPIOx->Pin, P7M0 |= GPIOx->Pin; //
+ }
+ return 0; // ɹ
+}
+void GPIO_config(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure; // ṹ
+
+ GPIO_InitStructure.Pin = GPIO_Pin_2; // ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7,
+ GPIO_InitStructure.Mode = GPIO_PullUp; // ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP
+ GPIO_Inilize(GPIO_P3, &GPIO_InitStructure); // ʼ
+ GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2; // ָҪʼIO, GPIO_Pin_0 ~ GPIO_Pin_7,
+ GPIO_InitStructure.Mode = GPIO_OUT_PP; // ָIOʽ,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP
+ GPIO_Inilize(GPIO_P1, &GPIO_InitStructure); // ʼ
+ power1_gpio = 0;
+ power2_gpio = 0;
+ power3_gpio = 0;
+}
\ No newline at end of file
diff --git a/mycode/main.c b/mycode/main.c
new file mode 100644
index 0000000..a4d0816
--- /dev/null
+++ b/mycode/main.c
@@ -0,0 +1,28 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* Ҫڳʹô˴,ڳעʹSTCϼ */
+/*---------------------------------------------------------------------*/
+
+#include "config.h"
+#include "GPIO.h"
+#include "Exti.h"
+#include "timer.h"
+
+/******************** ***********************/
+void main(void)
+{
+ GPIO_config();
+ Exti_config();
+ Timer_config();
+ EA = 1;
+ while (1)
+ {
+ }
+}
diff --git a/mycode/timer.c b/mycode/timer.c
new file mode 100644
index 0000000..292aa47
--- /dev/null
+++ b/mycode/timer.c
@@ -0,0 +1,176 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* Ҫڳʹô˴,ڳעʹSTCϼ */
+/*---------------------------------------------------------------------*/
+
+/************* ˵ **************
+
+ļΪSTC8ϵеĶʱʼжϳ,ûļԼҪжϳ.
+
+******************************************/
+
+#include "timer.h"
+u8 KILL_time = 0;
+/********************* Timer0жϺ************************/
+void timer0_int (void) interrupt TIMER0_VECTOR
+{
+ if (KILL_time)
+ {
+ KILL_time--;
+ }
+}
+
+/********************* Timer1жϺ************************/
+void timer1_int (void) interrupt TIMER1_VECTOR
+{
+
+}
+
+/********************* Timer2жϺ************************/
+void timer2_int (void) interrupt TIMER2_VECTOR
+{
+
+}
+
+/********************* Timer3жϺ************************/
+void timer3_int (void) interrupt TIMER3_VECTOR
+{
+
+}
+
+/********************* Timer4жϺ************************/
+void timer4_int (void) interrupt TIMER4_VECTOR
+{
+
+}
+
+
+//========================================================================
+// : u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx)
+// : ʱʼ.
+// : TIMx: ṹ,οtimer.hĶ.
+// : ɹ0, ղ1,2.
+// 汾: V1.0, 2012-10-22
+//========================================================================
+u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx)
+{
+ if(TIM > Timer4) return 1; //ղ
+
+ if(TIM == Timer0)
+ {
+ Timer0_Stop(); //ֹͣ
+ if(TIMx->TIM_Interrupt == ENABLE) Timer0_InterruptEnable(); //ж
+ else Timer0_InterruptDisable(); //ֹж
+ if(TIMx->TIM_Priority > Priority_3) return 2; //
+ Timer0_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3
+
+ if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //
+ TMOD = (TMOD & ~0x03) | TIMx->TIM_Mode; //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ, 3: 16λԶװ
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer0_12T(); //12T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer0_1T(); //1T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer0_AsCounter(); //Ƶ
+ else Timer0_AsTimer(); //ʱ
+ if(TIMx->TIM_ClkOut == ENABLE) Timer0_CLKO_Enable(); //ʱ
+ else Timer0_CLKO_Disable(); //ʱ
+
+ T0_Load(TIMx->TIM_Value);
+ if(TIMx->TIM_Run == ENABLE) Timer0_Run(); //ʼ
+ return 0; //ɹ
+ }
+
+ if(TIM == Timer1)
+ {
+ Timer1_Stop(); //ֹͣ
+ if(TIMx->TIM_Interrupt == ENABLE) Timer1_InterruptEnable(); //ж
+ else Timer1_InterruptDisable(); //ֹж
+ if(TIMx->TIM_Priority > Priority_3) return 2; //
+ Timer1_Priority(TIMx->TIM_Priority); //ָжȼ(͵) Priority_0,Priority_1,Priority_2,Priority_3
+ if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //
+ TMOD = (TMOD & ~0x30) | (TIMx->TIM_Mode<<4); //ģʽ,0: 16λԶװ, 1: 16λʱ/, 2: 8λԶװ, 3: ֹͣ
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer1_12T(); //12T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer1_1T(); //1T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer1_AsCounter(); //Ƶ
+ else Timer1_AsTimer(); //ʱ
+ if(TIMx->TIM_ClkOut == ENABLE) Timer1_CLKO_Enable(); //ʱ
+ else Timer1_CLKO_Disable(); //ʱ
+
+ T1_Load(TIMx->TIM_Value);
+ if(TIMx->TIM_Run == ENABLE) Timer1_Run(); //ʼ
+ return 0; //ɹ
+ }
+
+ if(TIM == Timer2) //Timer2,̶Ϊ16λԶװ, жȼ
+ {
+ Timer2_Stop(); //ֹͣ
+ if(TIMx->TIM_Interrupt == ENABLE) Timer2_InterruptEnable(); //ж
+ else Timer2_InterruptDisable(); //ֹж
+ if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2;
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer2_12T(); //12T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer2_1T(); //1T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer2_AsCounter(); //Ƶ
+ else Timer2_AsTimer(); //ʱ
+ if(TIMx->TIM_ClkOut == ENABLE) Timer2_CLKO_Enable(); //ʱ
+ else Timer2_CLKO_Disable(); //ʱ
+
+ T2_Load(TIMx->TIM_Value);
+ if(TIMx->TIM_Run == ENABLE) Timer2_Run(); //ʼ
+ return 0; //ɹ
+ }
+
+ if(TIM == Timer3) //Timer3,̶Ϊ16λԶװ, жȼ
+ {
+ Timer3_Stop(); //ֹͣ
+ if(TIMx->TIM_Interrupt == ENABLE) Timer3_InterruptEnable(); //ж
+ else Timer3_InterruptDisable(); //ֹж
+ if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2;
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer3_12T(); //12T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer3_1T(); //1T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer3_AsCounter(); //Ƶ
+ else Timer3_AsTimer(); //ʱ
+ if(TIMx->TIM_ClkOut == ENABLE) Timer3_CLKO_Enable(); //ʱ
+ else Timer3_CLKO_Disable(); //ʱ
+
+ T3_Load(TIMx->TIM_Value);
+ if(TIMx->TIM_Run == ENABLE) Timer3_Run(); //ʼ
+ return 0; //ɹ
+ }
+
+ if(TIM == Timer4) //Timer3,̶Ϊ16λԶװ, жȼ
+ {
+ Timer4_Stop(); //ֹͣ
+ if(TIMx->TIM_Interrupt == ENABLE) Timer4_InterruptEnable(); //ж
+ else Timer4_InterruptDisable(); //ֹж
+ if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2;
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer4_12T(); //12T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer4_1T(); //1T
+ if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer4_AsCounter(); //Ƶ
+ else Timer4_AsTimer(); //ʱ
+ if(TIMx->TIM_ClkOut == ENABLE) Timer4_CLKO_Enable(); //ʱ
+ else Timer4_CLKO_Disable(); //ʱ
+
+ T4_Load(TIMx->TIM_Value);
+ if(TIMx->TIM_Run == ENABLE) Timer4_Run(); //ʼ
+ return 0; //ɹ
+ }
+ return 2; //
+}
+/************************ ??????? ****************************/
+void Timer_config(void)
+{
+ TIM_InitTypeDef TIM_InitStructure;
+ TIM_InitStructure.TIM_Mode = TIM_16BitAutoReload;
+ TIM_InitStructure.TIM_Priority = Priority_0;
+ TIM_InitStructure.TIM_Interrupt = ENABLE;
+ TIM_InitStructure.TIM_ClkSource = TIM_CLOCK_1T;
+ TIM_InitStructure.TIM_ClkOut = DISABLE;
+ TIM_InitStructure.TIM_Value = 65536UL - (MAIN_Fosc / 1000UL);
+ TIM_InitStructure.TIM_Run = ENABLE;
+ Timer_Inilize(Timer0,&TIM_InitStructure);
+}
\ No newline at end of file
diff --git a/myinc/Exti.h b/myinc/Exti.h
new file mode 100644
index 0000000..d660b79
--- /dev/null
+++ b/myinc/Exti.h
@@ -0,0 +1,38 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* ���Ҫ�ڳ�����ʹ�ô˴���,���ڳ�����ע��ʹ����STC�����ϼ����� */
+/*---------------------------------------------------------------------*/
+
+#ifndef __EXTI_H
+#define __EXTI_H
+
+#include "config.h"
+#include "GPIO.h"
+#include "timer.h"
+
+#define EXT_INT0 0 // ��ʼ�����ж�0
+#define EXT_INT1 1 // ��ʼ�����ж�1
+#define EXT_INT2 2 // ��ʼ�����ж�2
+#define EXT_INT3 3 // ��ʼ�����ж�3
+#define EXT_INT4 4 // ��ʼ�����ж�4
+
+#define EXT_MODE_RiseFall 0 // ������/�½����ж�
+#define EXT_MODE_Fall 1 // �½����ж�
+
+typedef struct
+{
+ u8 EXTI_Mode; // �ж�ģʽ, EXT_MODE_RiseFall, EXT_MODE_Fall
+ u8 EXTI_Priority; // ���ȼ����� Priority_0,Priority_1,Priority_2,Priority_3
+ u8 EXTI_Interrupt; // ����� ENABLE,DISABLE
+} EXTI_InitTypeDef;
+
+u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx);
+void Exti_config(void);
+#endif
diff --git a/myinc/GPIO.h b/myinc/GPIO.h
new file mode 100644
index 0000000..f1d9c72
--- /dev/null
+++ b/myinc/GPIO.h
@@ -0,0 +1,53 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* Ҫڳʹô˴,ڳעʹSTCϼ */
+/*---------------------------------------------------------------------*/
+
+#ifndef __GPIO_H
+#define __GPIO_H
+
+#include "config.h"
+
+#define GPIO_PullUp 0 //˫
+#define GPIO_HighZ 1 //
+#define GPIO_OUT_OD 2 //©
+#define GPIO_OUT_PP 3 //
+
+#define GPIO_Pin_0 0x01 //IO Px.0
+#define GPIO_Pin_1 0x02 //IO Px.1
+#define GPIO_Pin_2 0x04 //IO Px.2
+#define GPIO_Pin_3 0x08 //IO Px.3
+#define GPIO_Pin_4 0x10 //IO Px.4
+#define GPIO_Pin_5 0x20 //IO Px.5
+#define GPIO_Pin_6 0x40 //IO Px.6
+#define GPIO_Pin_7 0x80 //IO Px.7
+#define GPIO_Pin_All 0xFF //IO
+
+#define GPIO_P0 0 //
+#define GPIO_P1 1
+#define GPIO_P2 2
+#define GPIO_P3 3
+#define GPIO_P4 4
+#define GPIO_P5 5
+#define GPIO_P6 6
+#define GPIO_P7 7
+#define kill_gpio P32
+#define power1_gpio P10
+#define power2_gpio P11
+#define power3_gpio P12
+typedef struct
+{
+ u8 Mode; //IOģʽ, GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP
+ u8 Pin; //ҪõĶ˿
+} GPIO_InitTypeDef;
+
+u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx);
+void GPIO_config(void);
+#endif
diff --git a/myinc/STC8xxxx.H b/myinc/STC8xxxx.H
new file mode 100644
index 0000000..18458c7
--- /dev/null
+++ b/myinc/STC8xxxx.H
@@ -0,0 +1,2747 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* Ҫڳʹô˴,ڳעʹSTCϼ */
+/*---------------------------------------------------------------------*/
+
+#ifndef _STC8xxxx_H
+#define _STC8xxxx_H
+
+#include
+
+/* BYTE Registers */
+sfr P0 = 0x80;
+sfr SP = 0x81;
+sfr DPL = 0x82;
+sfr DPH = 0x83;
+sfr S4CON = 0x84;
+sfr S4BUF = 0x85;
+sfr PCON = 0x87;
+
+sfr TCON = 0x88;
+sfr TMOD = 0x89;
+sfr TL0 = 0x8A;
+sfr TL1 = 0x8B;
+sfr TH0 = 0x8C;
+sfr TH1 = 0x8D;
+sfr AUXR = 0x8E;
+sfr WAKE_CLKO = 0x8F;
+sfr INT_CLKO = 0x8F;
+
+sfr P1 = 0x90;
+sfr P1M1 = 0x91; //P1M1.n,P1M0.n =00--->Standard, 01--->push-pull ʵ1TĶһ
+sfr P1M0 = 0x92; // =10--->pure input, 11--->open drain
+sfr P0M1 = 0x93; //P0M1.n,P0M0.n =00--->Standard, 01--->push-pull
+sfr P0M0 = 0x94; // =10--->pure input, 11--->open drain
+sfr P2M1 = 0x95; //P2M1.n,P2M0.n =00--->Standard, 01--->push-pull
+sfr P2M0 = 0x96; // =10--->pure input, 11--->open drain
+//sfr PCON2 = 0x97;
+//sfr AUXR2 = 0x97;
+
+sfr SCON = 0x98;
+sfr SBUF = 0x99;
+sfr S2CON = 0x9A; //
+sfr S2BUF = 0x9B; //
+
+sfr P2 = 0xA0;
+sfr BUS_SPEED = 0xA1;
+sfr P_SW1 = 0xA2;
+
+sfr IE = 0xA8;
+sfr SADDR = 0xA9;
+sfr WKTCL = 0xAA; //Ѷʱֽ
+sfr WKTCH = 0xAB; //Ѷʱֽ
+sfr S3CON = 0xAC;
+sfr S3BUF = 0xAD;
+sfr TA = 0xAE;
+sfr IE2 = 0xAF;
+
+sfr P3 = 0xB0;
+sfr P3M1 = 0xB1; //P3M1.n,P3M0.n =00--->Standard, 01--->push-pull
+sfr P3M0 = 0xB2; // =10--->pure input, 11--->open drain
+sfr P4M1 = 0xB3; //P4M1.n,P4M0.n =00--->Standard, 01--->push-pull
+sfr P4M0 = 0xB4; // =10--->pure input, 11--->open drain
+sfr IP2 = 0xB5;
+sfr IP2H = 0xB6;
+sfr IPH = 0xB7;
+
+sfr IP = 0xB8;
+sfr SADEN = 0xB9;
+sfr P_SW2 = 0xBA;
+sfr VOCTRL = 0xBB;
+sfr ADC_CONTR = 0xBC; //ADCƼĴ
+sfr ADC_RES = 0xBD; //ADCֽ
+sfr ADC_RESL = 0xBE; //ADCֽ
+
+sfr P4 = 0xC0;
+sfr WDT_CONTR = 0xC1;
+
+sfr IAP_DATA = 0xC2;
+sfr IAP_ADDRH = 0xC3;
+sfr IAP_ADDRL = 0xC4;
+sfr IAP_CMD = 0xC5;
+sfr IAP_TRIG = 0xC6;
+sfr IAP_CONTR = 0xC7;
+
+sfr ISP_DATA = 0xC2;
+sfr ISP_ADDRH = 0xC3;
+sfr ISP_ADDRL = 0xC4;
+sfr ISP_CMD = 0xC5;
+sfr ISP_TRIG = 0xC6;
+sfr ISP_CONTR = 0xC7;
+
+sfr P5 = 0xC8; //
+sfr P5M1 = 0xC9; // P5M1.n,P5M0.n =00--->Standard, 01--->push-pull
+sfr P5M0 = 0xCA; // =10--->pure input, 11--->open drain
+sfr P6M1 = 0xCB; // P5M1.n,P5M0.n =00--->Standard, 01--->push-pull
+sfr P6M0 = 0xCC; // =10--->pure input, 11--->open drain
+sfr SPSTAT = 0xCD; //
+sfr SPCTL = 0xCE; //
+sfr SPDAT = 0xCF; //
+
+sfr PSW = 0xD0;
+sfr T4T3M = 0xD1;
+sfr T4H = 0xD2;
+sfr T4L = 0xD3;
+sfr T3H = 0xD4;
+sfr T3L = 0xD5;
+sfr T2H = 0xD6;
+sfr T2L = 0xD7;
+
+sfr TH4 = 0xD2;
+sfr TL4 = 0xD3;
+sfr TH3 = 0xD4;
+sfr TL3 = 0xD5;
+sfr TH2 = 0xD6;
+sfr TL2 = 0xD7;
+
+sfr CCON = 0xD8; //
+sfr CMOD = 0xD9; //
+sfr CCAPM0 = 0xDA; //PCAģ0ĹģʽĴ
+sfr CCAPM1 = 0xDB; //PCAģ1ĹģʽĴ
+sfr CCAPM2 = 0xDC; //PCAģ2ĹģʽĴ
+//sfr CCAPM3 = 0xDD; //PCAģ3ĹģʽĴ
+sfr USBCLK = 0xDC;
+sfr ADCCFG = 0xDE; //
+sfr IP3 = 0xDF; //жȼĴ
+
+sfr ACC = 0xE0;
+sfr P7M1 = 0xE1;
+sfr P7M0 = 0xE2;
+sfr DPS = 0xE3;
+sfr DPL1 = 0xE4;
+sfr DPH1 = 0xE5;
+sfr CMPCR1 = 0xE6;
+sfr CMPCR2 = 0xE7;
+
+sfr P6 = 0xE8;
+sfr CL = 0xE9; //
+sfr CCAP0L = 0xEA; //PCAģ0IJ/ȽϼĴ8λ
+sfr CCAP1L = 0xEB; //PCAģ1IJ/ȽϼĴ8λ
+sfr CCAP2L = 0xEC; //PCAģ2IJ/ȽϼĴ8λ
+//sfr CCAP3L = 0xED; //PCAģ3IJ/ȽϼĴ8λ
+sfr USBDAT = 0xEC;
+sfr IP3H = 0xEE;
+sfr AUXINTIF = 0xEF; //жϱ־ B6-INT4IF, B5-INT3IF, B4-INT2IF, B2-T4IF, B1-T3IF, B0-T2IF
+
+sfr B = 0xF0;
+sfr PWMSET = 0xF1; //ǿPWMȫüĴ
+sfr PCA_PWM0 = 0xF2; //PCAģ0 PWMĴ
+sfr PCA_PWM1 = 0xF3; //PCAģ1 PWMĴ
+sfr PCA_PWM2 = 0xF4; //PCAģ2 PWMĴ
+//sfr PCA_PWM3 = 0xF5; //PCAģ3 PWMĴ
+sfr PWMCFG01 = 0xF6; //ǿPWMüĴ
+sfr PWMCFG23 = 0xF7; //ǿPWMüĴ
+sfr USBCON = 0xF4;
+sfr IAP_TPS = 0xF5;
+
+sfr P7 = 0xF8;
+sfr CH = 0xF9;
+sfr CCAP0H = 0xFA; //PCAģ0IJ/ȽϼĴ8λ
+sfr CCAP1H = 0xFB; //PCAģ1IJ/ȽϼĴ8λ
+sfr CCAP2H = 0xFC; //PCAģ2IJ/ȽϼĴ8λ
+//sfr CCAP3H = 0xFD; //PCAģ3IJ/ȽϼĴ8λ
+sfr PWMCFG45 = 0xFE; //ǿPWMüĴ
+sfr USBADR = 0xFC;
+sfr RSTCFG = 0xFF; //
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//INT_CLKO: жʱƼĴ - EX4 EX3 EX2 - T2CLKO T1CLKO T0CLKO 0000,0000
+#define INT4_Enable() INT_CLKO |= (1 << 6)
+#define INT3_Enable() INT_CLKO |= (1 << 5)
+#define INT2_Enable() INT_CLKO |= (1 << 4)
+#define INT1_Enable() EX1 = 1
+#define INT0_Enable() EX0 = 1
+
+#define INT4_Disable() INT_CLKO &= ~(1 << 6)
+#define INT3_Disable() INT_CLKO &= ~(1 << 5)
+#define INT2_Disable() INT_CLKO &= ~(1 << 4)
+#define INT1_Disable() EX1 = 0
+#define INT0_Disable() EX0 = 0
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//AUXINTIF: жϱ־Ĵ - INT4IF INT3IF INT2IF - T4IF T3IF T2IF 0000,0000
+#define INT4IF 0x40
+#define INT3IF 0x20
+#define INT2IF 0x10
+#define T4IF 0x04
+#define T3IF 0x02
+#define T2IF 0x01
+
+#define INT4_Clear() AUXINTIF &= ~INT4IF /* ж4־λ */
+#define INT3_Clear() AUXINTIF &= ~INT3IF /* ж3־λ */
+#define INT2_Clear() AUXINTIF &= ~INT2IF /* ж2־λ */
+#define INT1_Clear() IE1 = 0 /* ж1־λ */
+#define INT0_Clear() IE0 = 0 /* ж0־λ */
+
+#define INT0_Fall() IT0 = 1 /* INT0 ½ж */
+#define INT0_RiseFall() IT0 = 0 /* INT0 ½ؾж */
+#define INT1_Fall() IT1 = 1 /* INT1 ½ж */
+#define INT1_RiseFall() IT0 = 0 /* INT1 ½ؾж */
+
+
+//===============================================================
+#define EAXSFR() P_SW2 |= 0x80 /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչSFR(XSFR) */
+#define EAXRAM() P_SW2 &= ~0x80 /* MOVX A,@DPTR/MOVX @DPTR,AָIJΪչRAM(XRAM) */
+
+#define I2C_USE_P14P15() P_SW2 &= ~0x30 /* I2CлP1.4(SDA) P1.5(SCL)(ϵĬ).*/
+#define I2C_USE_P24P25() P_SW2 = (P_SW2 & ~0x30) | 0x10 /* I2CлP2.4(SDA) P2.5(SCL).*/
+#define I2C_USE_P76P77() P_SW2 = (P_SW2 & ~0x30) | 0x20 /* I2CлP7.6(SDA) P7.7(SCL).*/
+#define I2C_USE_P33P32() P_SW2 |= 0x30 /* I2CлP3.3(SDA) P3.2(SCL).*/
+
+#define CLKSEL (*(unsigned char volatile xdata *)0xfe00)
+#define CKSEL (*(unsigned char volatile xdata *)0xfe00) /* ʱԴѡ */
+#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) /* ʱӷƵ */
+#define IRC24MCR (*(unsigned char volatile xdata *)0xfe02) /* IRC 24MHZ */
+#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) /* XOSC */
+#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) /* IRC 32KHZ */
+#define MCLKOCR (*(unsigned char volatile xdata *)0xfe05)
+#define IRCDB (*(unsigned char volatile xdata *)0xfe06)
+#define X32KCR (*(unsigned char volatile xdata *)0xfe08)
+
+#define MainFosc_IRC24M() CKSEL = (CKSEL & ~0x03) /* ѡڲ24MHZʱ */
+#define MainFosc_XTAL() CKSEL = (CKSEL & ~0x03) | 0x01 /* ѡⲿʱ */
+#define MainFosc_IRC32K() CKSEL = CKSEL | 0x03 /* ѡڲ32Kʱ */
+#define EXT_CLOCK() XOSCCR = 0x80 /* ѡⲿʱ */
+#define EXT_CRYSTAL() XOSCCR = 0xC0 /* ѡⲿ */
+
+
+#define P0PU (*(unsigned char volatile xdata *)0xfe10) /* P0 4.1K Pull Up Enable */
+#define P1PU (*(unsigned char volatile xdata *)0xfe11) /* P1 4.1K Pull Up Enable */
+#define P2PU (*(unsigned char volatile xdata *)0xfe12) /* P2 4.1K Pull Up Enable */
+#define P3PU (*(unsigned char volatile xdata *)0xfe13) /* P3 4.1K Pull Up Enable */
+#define P4PU (*(unsigned char volatile xdata *)0xfe14) /* P4 4.1K Pull Up Enable */
+#define P5PU (*(unsigned char volatile xdata *)0xfe15) /* P5 4.1K Pull Up Enable */
+#define P6PU (*(unsigned char volatile xdata *)0xfe16) /* P6 4.1K Pull Up Enable */
+#define P7PU (*(unsigned char volatile xdata *)0xfe17) /* P7 4.1K Pull Up Enable */
+
+#define P0NCS (*(unsigned char volatile xdata *)0xfe18) /* P0 Non Schmit Trigger 0: ʹܶ˿ʩش(Ĭ), 1: ֹ */
+#define P1NCS (*(unsigned char volatile xdata *)0xfe19) /* P1 Non Schmit Trigger */
+#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) /* P2 Non Schmit Trigger */
+#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) /* P3 Non Schmit Trigger */
+#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) /* P4 Non Schmit Trigger */
+#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) /* P5 Non Schmit Trigger */
+#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) /* P6 Non Schmit Trigger */
+#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) /* P7 Non Schmit Trigger */
+
+#define P0SR (*(unsigned char volatile xdata *)0xfe20) /* ˿ڵƽתٶ 0: , 1: (Ĭ) */
+#define P1SR (*(unsigned char volatile xdata *)0xfe21)
+#define P2SR (*(unsigned char volatile xdata *)0xfe22)
+#define P3SR (*(unsigned char volatile xdata *)0xfe23)
+#define P4SR (*(unsigned char volatile xdata *)0xfe24)
+#define P5SR (*(unsigned char volatile xdata *)0xfe25)
+#define P6SR (*(unsigned char volatile xdata *)0xfe26)
+#define P7SR (*(unsigned char volatile xdata *)0xfe27)
+
+#define P0DR (*(unsigned char volatile xdata *)0xfe28) /* ˿ 0: ǿ, 1: һ(Ĭ) */
+#define P1DR (*(unsigned char volatile xdata *)0xfe29)
+#define P2DR (*(unsigned char volatile xdata *)0xfe2a)
+#define P3DR (*(unsigned char volatile xdata *)0xfe2b)
+#define P4DR (*(unsigned char volatile xdata *)0xfe2c)
+#define P5DR (*(unsigned char volatile xdata *)0xfe2d)
+#define P6DR (*(unsigned char volatile xdata *)0xfe2e)
+#define P7DR (*(unsigned char volatile xdata *)0xfe2f)
+
+#define P0IE (*(unsigned char volatile xdata *)0xfe30)/* ˿źʹ 0: ֹź, 1: ʹź(Ĭ) */
+#define P1IE (*(unsigned char volatile xdata *)0xfe31)
+#define P2IE (*(unsigned char volatile xdata *)0xfe32)
+#define P3IE (*(unsigned char volatile xdata *)0xfe33)
+#define P4IE (*(unsigned char volatile xdata *)0xfe34)
+#define P5IE (*(unsigned char volatile xdata *)0xfe35)
+#define P6IE (*(unsigned char volatile xdata *)0xfe36)
+#define P7IE (*(unsigned char volatile xdata *)0xfe37)
+
+#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) /* */
+#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) /* */
+#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) /* */
+#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) /* */
+#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) /* */
+#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) /* */
+#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) /* */
+#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) /* */
+#define I2CMSAUX (*(unsigned char volatile xdata *)0xfe88)
+
+#define TM2PS (*(unsigned char volatile xdata *)0xfea2)
+#define TM3PS (*(unsigned char volatile xdata *)0xfea3)
+#define TM4PS (*(unsigned char volatile xdata *)0xfea4)
+#define ADCTIM (*(unsigned char volatile xdata *)0xfea8)
+#define T3T4PIN (*(unsigned char volatile xdata *)0xfeac)
+
+#define PWMA_ETRPS (*(unsigned char volatile xdata *)0xfeb0)
+#define PWMA_ENO (*(unsigned char volatile xdata *)0xfeb1)
+#define PWMA_PS (*(unsigned char volatile xdata *)0xfeb2)
+#define PWMA_IOAUX (*(unsigned char volatile xdata *)0xfeb3)
+#define PWMB_ETRPS (*(unsigned char volatile xdata *)0xfeb4)
+#define PWMB_ENO (*(unsigned char volatile xdata *)0xfeb5)
+#define PWMB_PS (*(unsigned char volatile xdata *)0xfeb6)
+#define PWMB_IOAUX (*(unsigned char volatile xdata *)0xfeb7)
+#define PWMA_CR1 (*(unsigned char volatile xdata *)0xfec0)
+#define PWMA_CR2 (*(unsigned char volatile xdata *)0xfec1)
+#define PWMA_SMCR (*(unsigned char volatile xdata *)0xfec2)
+#define PWMA_ETR (*(unsigned char volatile xdata *)0xfec3)
+#define PWMA_IER (*(unsigned char volatile xdata *)0xfec4)
+#define PWMA_SR1 (*(unsigned char volatile xdata *)0xfec5)
+#define PWMA_SR2 (*(unsigned char volatile xdata *)0xfec6)
+#define PWMA_EGR (*(unsigned char volatile xdata *)0xfec7)
+#define PWMA_CCMR1 (*(unsigned char volatile xdata *)0xfec8)
+#define PWMA_CCMR2 (*(unsigned char volatile xdata *)0xfec9)
+#define PWMA_CCMR3 (*(unsigned char volatile xdata *)0xfeca)
+#define PWMA_CCMR4 (*(unsigned char volatile xdata *)0xfecb)
+#define PWMA_CCER1 (*(unsigned char volatile xdata *)0xfecc)
+#define PWMA_CCER2 (*(unsigned char volatile xdata *)0xfecd)
+#define PWMA_CNTR (*(unsigned int volatile xdata *)0xfece)
+#define PWMA_CNTRH (*(unsigned char volatile xdata *)0xfece)
+#define PWMA_CNTRL (*(unsigned char volatile xdata *)0xfecf)
+#define PWMA_PSCR (*(unsigned int volatile xdata *)0xfed0)
+#define PWMA_PSCRH (*(unsigned char volatile xdata *)0xfed0)
+#define PWMA_PSCRL (*(unsigned char volatile xdata *)0xfed1)
+#define PWMA_ARR (*(unsigned int volatile xdata *)0xfed2)
+#define PWMA_ARRH (*(unsigned char volatile xdata *)0xfed2)
+#define PWMA_ARRL (*(unsigned char volatile xdata *)0xfed3)
+#define PWMA_RCR (*(unsigned char volatile xdata *)0xfed4)
+#define PWMA_CCR1 (*(unsigned int volatile xdata *)0xfed5)
+#define PWMA_CCR1H (*(unsigned char volatile xdata *)0xfed5)
+#define PWMA_CCR1L (*(unsigned char volatile xdata *)0xfed6)
+#define PWMA_CCR2 (*(unsigned int volatile xdata *)0xfed7)
+#define PWMA_CCR2H (*(unsigned char volatile xdata *)0xfed7)
+#define PWMA_CCR2L (*(unsigned char volatile xdata *)0xfed8)
+#define PWMA_CCR3 (*(unsigned int volatile xdata *)0xfed9)
+#define PWMA_CCR3H (*(unsigned char volatile xdata *)0xfed9)
+#define PWMA_CCR3L (*(unsigned char volatile xdata *)0xfeda)
+#define PWMA_CCR4 (*(unsigned int volatile xdata *)0xfedb)
+#define PWMA_CCR4H (*(unsigned char volatile xdata *)0xfedb)
+#define PWMA_CCR4L (*(unsigned char volatile xdata *)0xfedc)
+#define PWMA_BRK (*(unsigned char volatile xdata *)0xfedd)
+#define PWMA_DTR (*(unsigned char volatile xdata *)0xfede)
+#define PWMA_OISR (*(unsigned char volatile xdata *)0xfedf)
+
+#define PWMB_CR1 (*(unsigned char volatile xdata *)0xfee0)
+#define PWMB_CR2 (*(unsigned char volatile xdata *)0xfee1)
+#define PWMB_SMCR (*(unsigned char volatile xdata *)0xfee2)
+#define PWMB_ETR (*(unsigned char volatile xdata *)0xfee3)
+#define PWMB_IER (*(unsigned char volatile xdata *)0xfee4)
+#define PWMB_SR1 (*(unsigned char volatile xdata *)0xfee5)
+#define PWMB_SR2 (*(unsigned char volatile xdata *)0xfee6)
+#define PWMB_EGR (*(unsigned char volatile xdata *)0xfee7)
+#define PWMB_CCMR1 (*(unsigned char volatile xdata *)0xfee8)
+#define PWMB_CCMR2 (*(unsigned char volatile xdata *)0xfee9)
+#define PWMB_CCMR3 (*(unsigned char volatile xdata *)0xfeea)
+#define PWMB_CCMR4 (*(unsigned char volatile xdata *)0xfeeb)
+#define PWMB_CCER1 (*(unsigned char volatile xdata *)0xfeec)
+#define PWMB_CCER2 (*(unsigned char volatile xdata *)0xfeed)
+#define PWMB_CNTR (*(unsigned int volatile xdata *)0xfeee)
+#define PWMB_CNTRH (*(unsigned char volatile xdata *)0xfeee)
+#define PWMB_CNTRL (*(unsigned char volatile xdata *)0xfeef)
+#define PWMB_PSCR (*(unsigned int volatile xdata *)0xfef0)
+#define PWMB_PSCRH (*(unsigned char volatile xdata *)0xfef0)
+#define PWMB_PSCRL (*(unsigned char volatile xdata *)0xfef1)
+#define PWMB_ARR (*(unsigned int volatile xdata *)0xfef2)
+#define PWMB_ARRH (*(unsigned char volatile xdata *)0xfef2)
+#define PWMB_ARRL (*(unsigned char volatile xdata *)0xfef3)
+#define PWMB_RCR (*(unsigned char volatile xdata *)0xfef4)
+#define PWMB_CCR5 (*(unsigned int volatile xdata *)0xfef5)
+#define PWMB_CCR5H (*(unsigned char volatile xdata *)0xfef5)
+#define PWMB_CCR5L (*(unsigned char volatile xdata *)0xfef6)
+#define PWMB_CCR6 (*(unsigned int volatile xdata *)0xfef7)
+#define PWMB_CCR6H (*(unsigned char volatile xdata *)0xfef7)
+#define PWMB_CCR6L (*(unsigned char volatile xdata *)0xfef8)
+#define PWMB_CCR7 (*(unsigned int volatile xdata *)0xfef9)
+#define PWMB_CCR7H (*(unsigned char volatile xdata *)0xfef9)
+#define PWMB_CCR7L (*(unsigned char volatile xdata *)0xfefa)
+#define PWMB_CCR8 (*(unsigned int volatile xdata *)0xfefb)
+#define PWMB_CCR8H (*(unsigned char volatile xdata *)0xfefb)
+#define PWMB_CCR8L (*(unsigned char volatile xdata *)0xfefc)
+#define PWMB_BRK (*(unsigned char volatile xdata *)0xfefd)
+#define PWMB_DTR (*(unsigned char volatile xdata *)0xfefe)
+#define PWMB_OISR (*(unsigned char volatile xdata *)0xfeff)
+
+/////////////////////////////////////////////////
+//FD00H-FDFFH
+/////////////////////////////////////////////////
+
+#define PWM0C (*(unsigned int volatile xdata *)0xff00)
+#define PWM0CH (*(unsigned char volatile xdata *)0xff00)
+#define PWM0CL (*(unsigned char volatile xdata *)0xff01)
+#define PWM0CKS (*(unsigned char volatile xdata *)0xff02)
+#define PWM0TADC (*(unsigned int volatile xdata *)0xff03)
+#define PWM0TADCH (*(unsigned char volatile xdata *)0xff03)
+#define PWM0TADCL (*(unsigned char volatile xdata *)0xff04)
+#define PWM0IF (*(unsigned char volatile xdata *)0xff05)
+#define PWM0FDCR (*(unsigned char volatile xdata *)0xff06)
+#define PWM00T1 (*(unsigned int volatile xdata *)0xff10)
+#define PWM00T1H (*(unsigned char volatile xdata *)0xff10)
+#define PWM00T1L (*(unsigned char volatile xdata *)0xff11)
+#define PWM00T2 (*(unsigned int volatile xdata *)0xff12)
+#define PWM00T2H (*(unsigned char volatile xdata *)0xff12)
+#define PWM00T2L (*(unsigned char volatile xdata *)0xff13)
+#define PWM00CR (*(unsigned char volatile xdata *)0xff14)
+#define PWM00HLD (*(unsigned char volatile xdata *)0xff15)
+#define PWM01T1 (*(unsigned int volatile xdata *)0xff18)
+#define PWM01T1H (*(unsigned char volatile xdata *)0xff18)
+#define PWM01T1L (*(unsigned char volatile xdata *)0xff19)
+#define PWM01T2 (*(unsigned int volatile xdata *)0xff1a)
+#define PWM01T2H (*(unsigned char volatile xdata *)0xff1a)
+#define PWM01T2L (*(unsigned char volatile xdata *)0xff1b)
+#define PWM01CR (*(unsigned char volatile xdata *)0xff1c)
+#define PWM01HLD (*(unsigned char volatile xdata *)0xff1d)
+#define PWM02T1 (*(unsigned int volatile xdata *)0xff20)
+#define PWM02T1H (*(unsigned char volatile xdata *)0xff20)
+#define PWM02T1L (*(unsigned char volatile xdata *)0xff21)
+#define PWM02T2 (*(unsigned int volatile xdata *)0xff22)
+#define PWM02T2H (*(unsigned char volatile xdata *)0xff22)
+#define PWM02T2L (*(unsigned char volatile xdata *)0xff23)
+#define PWM02CR (*(unsigned char volatile xdata *)0xff24)
+#define PWM02HLD (*(unsigned char volatile xdata *)0xff25)
+#define PWM03T1 (*(unsigned int volatile xdata *)0xff28)
+#define PWM03T1H (*(unsigned char volatile xdata *)0xff28)
+#define PWM03T1L (*(unsigned char volatile xdata *)0xff29)
+#define PWM03T2 (*(unsigned int volatile xdata *)0xff2a)
+#define PWM03T2H (*(unsigned char volatile xdata *)0xff2a)
+#define PWM03T2L (*(unsigned char volatile xdata *)0xff2b)
+#define PWM03CR (*(unsigned char volatile xdata *)0xff2c)
+#define PWM03HLD (*(unsigned char volatile xdata *)0xff2d)
+#define PWM04T1 (*(unsigned int volatile xdata *)0xff30)
+#define PWM04T1H (*(unsigned char volatile xdata *)0xff30)
+#define PWM04T1L (*(unsigned char volatile xdata *)0xff31)
+#define PWM04T2 (*(unsigned int volatile xdata *)0xff32)
+#define PWM04T2H (*(unsigned char volatile xdata *)0xff32)
+#define PWM04T2L (*(unsigned char volatile xdata *)0xff33)
+#define PWM04CR (*(unsigned char volatile xdata *)0xff34)
+#define PWM04HLD (*(unsigned char volatile xdata *)0xff35)
+#define PWM05T1 (*(unsigned int volatile xdata *)0xff38)
+#define PWM05T1H (*(unsigned char volatile xdata *)0xff38)
+#define PWM05T1L (*(unsigned char volatile xdata *)0xff39)
+#define PWM05T2 (*(unsigned int volatile xdata *)0xff3a)
+#define PWM05T2H (*(unsigned char volatile xdata *)0xff3a)
+#define PWM05T2L (*(unsigned char volatile xdata *)0xff3b)
+#define PWM05CR (*(unsigned char volatile xdata *)0xff3c)
+#define PWM05HLD (*(unsigned char volatile xdata *)0xff3d)
+#define PWM06T1 (*(unsigned int volatile xdata *)0xff40)
+#define PWM06T1H (*(unsigned char volatile xdata *)0xff40)
+#define PWM06T1L (*(unsigned char volatile xdata *)0xff41)
+#define PWM06T2 (*(unsigned int volatile xdata *)0xff42)
+#define PWM06T2H (*(unsigned char volatile xdata *)0xff42)
+#define PWM06T2L (*(unsigned char volatile xdata *)0xff43)
+#define PWM06CR (*(unsigned char volatile xdata *)0xff44)
+#define PWM06HLD (*(unsigned char volatile xdata *)0xff45)
+#define PWM07T1 (*(unsigned int volatile xdata *)0xff48)
+#define PWM07T1H (*(unsigned char volatile xdata *)0xff48)
+#define PWM07T1L (*(unsigned char volatile xdata *)0xff49)
+#define PWM07T2 (*(unsigned int volatile xdata *)0xff4a)
+#define PWM07T2H (*(unsigned char volatile xdata *)0xff4a)
+#define PWM07T2L (*(unsigned char volatile xdata *)0xff4b)
+#define PWM07CR (*(unsigned char volatile xdata *)0xff4c)
+#define PWM07HLD (*(unsigned char volatile xdata *)0xff4d)
+#define PWM1C (*(unsigned int volatile xdata *)0xff50)
+#define PWM1CH (*(unsigned char volatile xdata *)0xff50)
+#define PWM1CL (*(unsigned char volatile xdata *)0xff51)
+#define PWM1CKS (*(unsigned char volatile xdata *)0xff52)
+#define PWM1IF (*(unsigned char volatile xdata *)0xff55)
+#define PWM1FDCR (*(unsigned char volatile xdata *)0xff56)
+#define PWM10T1 (*(unsigned int volatile xdata *)0xff60)
+#define PWM10T1H (*(unsigned char volatile xdata *)0xff60)
+#define PWM10T1L (*(unsigned char volatile xdata *)0xff61)
+#define PWM10T2 (*(unsigned int volatile xdata *)0xff62)
+#define PWM10T2H (*(unsigned char volatile xdata *)0xff62)
+#define PWM10T2L (*(unsigned char volatile xdata *)0xff63)
+#define PWM10CR (*(unsigned char volatile xdata *)0xff64)
+#define PWM10HLD (*(unsigned char volatile xdata *)0xff65)
+#define PWM11T1 (*(unsigned int volatile xdata *)0xff68)
+#define PWM11T1H (*(unsigned char volatile xdata *)0xff68)
+#define PWM11T1L (*(unsigned char volatile xdata *)0xff69)
+#define PWM11T2 (*(unsigned int volatile xdata *)0xff6a)
+#define PWM11T2H (*(unsigned char volatile xdata *)0xff6a)
+#define PWM11T2L (*(unsigned char volatile xdata *)0xff6b)
+#define PWM11CR (*(unsigned char volatile xdata *)0xff6c)
+#define PWM11HLD (*(unsigned char volatile xdata *)0xff6d)
+#define PWM12T1 (*(unsigned int volatile xdata *)0xff70)
+#define PWM12T1H (*(unsigned char volatile xdata *)0xff70)
+#define PWM12T1L (*(unsigned char volatile xdata *)0xff71)
+#define PWM12T2 (*(unsigned int volatile xdata *)0xff72)
+#define PWM12T2H (*(unsigned char volatile xdata *)0xff72)
+#define PWM12T2L (*(unsigned char volatile xdata *)0xff73)
+#define PWM12CR (*(unsigned char volatile xdata *)0xff74)
+#define PWM12HLD (*(unsigned char volatile xdata *)0xff75)
+#define PWM13T1 (*(unsigned int volatile xdata *)0xff78)
+#define PWM13T1H (*(unsigned char volatile xdata *)0xff78)
+#define PWM13T1L (*(unsigned char volatile xdata *)0xff79)
+#define PWM13T2 (*(unsigned int volatile xdata *)0xff7a)
+#define PWM13T2H (*(unsigned char volatile xdata *)0xff7a)
+#define PWM13T2L (*(unsigned char volatile xdata *)0xff7b)
+#define PWM13CR (*(unsigned char volatile xdata *)0xff7c)
+#define PWM13HLD (*(unsigned char volatile xdata *)0xff7d)
+#define PWM14T1 (*(unsigned int volatile xdata *)0xff80)
+#define PWM14T1H (*(unsigned char volatile xdata *)0xff80)
+#define PWM14T1L (*(unsigned char volatile xdata *)0xff81)
+#define PWM14T2 (*(unsigned int volatile xdata *)0xff82)
+#define PWM14T2H (*(unsigned char volatile xdata *)0xff82)
+#define PWM14T2L (*(unsigned char volatile xdata *)0xff83)
+#define PWM14CR (*(unsigned char volatile xdata *)0xff84)
+#define PWM14HLD (*(unsigned char volatile xdata *)0xff85)
+#define PWM15T1 (*(unsigned int volatile xdata *)0xff88)
+#define PWM15T1H (*(unsigned char volatile xdata *)0xff88)
+#define PWM15T1L (*(unsigned char volatile xdata *)0xff89)
+#define PWM15T2 (*(unsigned int volatile xdata *)0xff8a)
+#define PWM15T2H (*(unsigned char volatile xdata *)0xff8a)
+#define PWM15T2L (*(unsigned char volatile xdata *)0xff8b)
+#define PWM15CR (*(unsigned char volatile xdata *)0xff8c)
+#define PWM15HLD (*(unsigned char volatile xdata *)0xff8d)
+#define PWM16T1 (*(unsigned int volatile xdata *)0xff90)
+#define PWM16T1H (*(unsigned char volatile xdata *)0xff90)
+#define PWM16T1L (*(unsigned char volatile xdata *)0xff91)
+#define PWM16T2 (*(unsigned int volatile xdata *)0xff92)
+#define PWM16T2H (*(unsigned char volatile xdata *)0xff92)
+#define PWM16T2L (*(unsigned char volatile xdata *)0xff93)
+#define PWM16CR (*(unsigned char volatile xdata *)0xff94)
+#define PWM16HLD (*(unsigned char volatile xdata *)0xff95)
+#define PWM17T1 (*(unsigned int volatile xdata *)0xff98)
+#define PWM17T1H (*(unsigned char volatile xdata *)0xff98)
+#define PWM17T1L (*(unsigned char volatile xdata *)0xff99)
+#define PWM17T2 (*(unsigned int volatile xdata *)0xff9a)
+#define PWM17T2H (*(unsigned char volatile xdata *)0xff9a)
+#define PWM17T2L (*(unsigned char volatile xdata *)0xff9b)
+#define PWM17CR (*(unsigned char volatile xdata *)0xff9c)
+#define PWM17HLD (*(unsigned char volatile xdata *)0xff9d)
+#define PWM2C (*(unsigned int volatile xdata *)0xffa0)
+#define PWM2CH (*(unsigned char volatile xdata *)0xffa0)
+#define PWM2CL (*(unsigned char volatile xdata *)0xffa1)
+#define PWM2CKS (*(unsigned char volatile xdata *)0xffa2)
+#define PWM2TADC (*(unsigned int volatile xdata *)0xffa3)
+#define PWM2TADCH (*(unsigned char volatile xdata *)0xffa3)
+#define PWM2TADCL (*(unsigned char volatile xdata *)0xffa4)
+#define PWM2IF (*(unsigned char volatile xdata *)0xffa5)
+#define PWM2FDCR (*(unsigned char volatile xdata *)0xffa6)
+#define PWM20T1 (*(unsigned int volatile xdata *)0xffb0)
+#define PWM20T1H (*(unsigned char volatile xdata *)0xffb0)
+#define PWM20T1L (*(unsigned char volatile xdata *)0xffb1)
+#define PWM20T2 (*(unsigned int volatile xdata *)0xffb2)
+#define PWM20T2H (*(unsigned char volatile xdata *)0xffb2)
+#define PWM20T2L (*(unsigned char volatile xdata *)0xffb3)
+#define PWM20CR (*(unsigned char volatile xdata *)0xffb4)
+#define PWM20HLD (*(unsigned char volatile xdata *)0xffb5)
+#define PWM21T1 (*(unsigned int volatile xdata *)0xffb8)
+#define PWM21T1H (*(unsigned char volatile xdata *)0xffb8)
+#define PWM21T1L (*(unsigned char volatile xdata *)0xffb9)
+#define PWM21T2 (*(unsigned int volatile xdata *)0xffba)
+#define PWM21T2H (*(unsigned char volatile xdata *)0xffba)
+#define PWM21T2L (*(unsigned char volatile xdata *)0xffbb)
+#define PWM21CR (*(unsigned char volatile xdata *)0xffbc)
+#define PWM21HLD (*(unsigned char volatile xdata *)0xffbd)
+#define PWM22T1 (*(unsigned int volatile xdata *)0xffc0)
+#define PWM22T1H (*(unsigned char volatile xdata *)0xffc0)
+#define PWM22T1L (*(unsigned char volatile xdata *)0xffc1)
+#define PWM22T2 (*(unsigned int volatile xdata *)0xffc2)
+#define PWM22T2H (*(unsigned char volatile xdata *)0xffc2)
+#define PWM22T2L (*(unsigned char volatile xdata *)0xffc3)
+#define PWM22CR (*(unsigned char volatile xdata *)0xffc4)
+#define PWM22HLD (*(unsigned char volatile xdata *)0xffc5)
+#define PWM23T1 (*(unsigned int volatile xdata *)0xffc8)
+#define PWM23T1H (*(unsigned char volatile xdata *)0xffc8)
+#define PWM23T1L (*(unsigned char volatile xdata *)0xffc9)
+#define PWM23T2 (*(unsigned int volatile xdata *)0xffca)
+#define PWM23T2H (*(unsigned char volatile xdata *)0xffca)
+#define PWM23T2L (*(unsigned char volatile xdata *)0xffcb)
+#define PWM23CR (*(unsigned char volatile xdata *)0xffcc)
+#define PWM23HLD (*(unsigned char volatile xdata *)0xffcd)
+#define PWM24T1 (*(unsigned int volatile xdata *)0xffd0)
+#define PWM24T1H (*(unsigned char volatile xdata *)0xffd0)
+#define PWM24T1L (*(unsigned char volatile xdata *)0xffd1)
+#define PWM24T2 (*(unsigned int volatile xdata *)0xffd2)
+#define PWM24T2H (*(unsigned char volatile xdata *)0xffd2)
+#define PWM24T2L (*(unsigned char volatile xdata *)0xffd3)
+#define PWM24CR (*(unsigned char volatile xdata *)0xffd4)
+#define PWM24HLD (*(unsigned char volatile xdata *)0xffd5)
+#define PWM25T1 (*(unsigned int volatile xdata *)0xffd8)
+#define PWM25T1H (*(unsigned char volatile xdata *)0xffd8)
+#define PWM25T1L (*(unsigned char volatile xdata *)0xffd9)
+#define PWM25T2 (*(unsigned int volatile xdata *)0xffda)
+#define PWM25T2H (*(unsigned char volatile xdata *)0xffda)
+#define PWM25T2L (*(unsigned char volatile xdata *)0xffdb)
+#define PWM25CR (*(unsigned char volatile xdata *)0xffdc)
+#define PWM25HLD (*(unsigned char volatile xdata *)0xffdd)
+#define PWM26T1 (*(unsigned int volatile xdata *)0xffe0)
+#define PWM26T1H (*(unsigned char volatile xdata *)0xffe0)
+#define PWM26T1L (*(unsigned char volatile xdata *)0xffe1)
+#define PWM26T2 (*(unsigned int volatile xdata *)0xffe2)
+#define PWM26T2H (*(unsigned char volatile xdata *)0xffe2)
+#define PWM26T2L (*(unsigned char volatile xdata *)0xffe3)
+#define PWM26CR (*(unsigned char volatile xdata *)0xffe4)
+#define PWM26HLD (*(unsigned char volatile xdata *)0xffe5)
+#define PWM27T1 (*(unsigned int volatile xdata *)0xffe8)
+#define PWM27T1H (*(unsigned char volatile xdata *)0xffe8)
+#define PWM27T1L (*(unsigned char volatile xdata *)0xffe9)
+#define PWM27T2 (*(unsigned int volatile xdata *)0xffea)
+#define PWM27T2H (*(unsigned char volatile xdata *)0xffea)
+#define PWM27T2L (*(unsigned char volatile xdata *)0xffeb)
+#define PWM27CR (*(unsigned char volatile xdata *)0xffec)
+#define PWM27HLD (*(unsigned char volatile xdata *)0xffed)
+
+/////////////////////////////////////////////////
+//FC00H-FCFFH
+/////////////////////////////////////////////////
+
+#define PWM3C (*(unsigned int volatile xdata *)0xfc00)
+#define PWM3CH (*(unsigned char volatile xdata *)0xfc00)
+#define PWM3CL (*(unsigned char volatile xdata *)0xfc01)
+#define PWM3CKS (*(unsigned char volatile xdata *)0xfc02)
+#define PWM3IF (*(unsigned char volatile xdata *)0xfc05)
+#define PWM3FDCR (*(unsigned char volatile xdata *)0xfc06)
+#define PWM30T1 (*(unsigned int volatile xdata *)0xfc10)
+#define PWM30T1H (*(unsigned char volatile xdata *)0xfc10)
+#define PWM30T1L (*(unsigned char volatile xdata *)0xfc11)
+#define PWM30T2 (*(unsigned int volatile xdata *)0xfc12)
+#define PWM30T2H (*(unsigned char volatile xdata *)0xfc12)
+#define PWM30T2L (*(unsigned char volatile xdata *)0xfc13)
+#define PWM30CR (*(unsigned char volatile xdata *)0xfc14)
+#define PWM30HLD (*(unsigned char volatile xdata *)0xfc15)
+#define PWM31T1 (*(unsigned int volatile xdata *)0xfc18)
+#define PWM31T1H (*(unsigned char volatile xdata *)0xfc18)
+#define PWM31T1L (*(unsigned char volatile xdata *)0xfc19)
+#define PWM31T2 (*(unsigned int volatile xdata *)0xfc1a)
+#define PWM31T2H (*(unsigned char volatile xdata *)0xfc1a)
+#define PWM31T2L (*(unsigned char volatile xdata *)0xfc1b)
+#define PWM31CR (*(unsigned char volatile xdata *)0xfc1c)
+#define PWM31HLD (*(unsigned char volatile xdata *)0xfc1d)
+#define PWM32T1 (*(unsigned int volatile xdata *)0xfc20)
+#define PWM32T1H (*(unsigned char volatile xdata *)0xfc20)
+#define PWM32T1L (*(unsigned char volatile xdata *)0xfc21)
+#define PWM32T2 (*(unsigned int volatile xdata *)0xfc22)
+#define PWM32T2H (*(unsigned char volatile xdata *)0xfc22)
+#define PWM32T2L (*(unsigned char volatile xdata *)0xfc23)
+#define PWM32CR (*(unsigned char volatile xdata *)0xfc24)
+#define PWM32HLD (*(unsigned char volatile xdata *)0xfc25)
+#define PWM33T1 (*(unsigned int volatile xdata *)0xfc28)
+#define PWM33T1H (*(unsigned char volatile xdata *)0xfc28)
+#define PWM33T1L (*(unsigned char volatile xdata *)0xfc29)
+#define PWM33T2 (*(unsigned int volatile xdata *)0xfc2a)
+#define PWM33T2H (*(unsigned char volatile xdata *)0xfc2a)
+#define PWM33T2L (*(unsigned char volatile xdata *)0xfc2b)
+#define PWM33CR (*(unsigned char volatile xdata *)0xfc2c)
+#define PWM33HLD (*(unsigned char volatile xdata *)0xfc2d)
+#define PWM34T1 (*(unsigned int volatile xdata *)0xfc30)
+#define PWM34T1H (*(unsigned char volatile xdata *)0xfc30)
+#define PWM34T1L (*(unsigned char volatile xdata *)0xfc31)
+#define PWM34T2 (*(unsigned int volatile xdata *)0xfc32)
+#define PWM34T2H (*(unsigned char volatile xdata *)0xfc32)
+#define PWM34T2L (*(unsigned char volatile xdata *)0xfc33)
+#define PWM34CR (*(unsigned char volatile xdata *)0xfc34)
+#define PWM34HLD (*(unsigned char volatile xdata *)0xfc35)
+#define PWM35T1 (*(unsigned int volatile xdata *)0xfc38)
+#define PWM35T1H (*(unsigned char volatile xdata *)0xfc38)
+#define PWM35T1L (*(unsigned char volatile xdata *)0xfc39)
+#define PWM35T2 (*(unsigned int volatile xdata *)0xfc3a)
+#define PWM35T2H (*(unsigned char volatile xdata *)0xfc3a)
+#define PWM35T2L (*(unsigned char volatile xdata *)0xfc3b)
+#define PWM35CR (*(unsigned char volatile xdata *)0xfc3c)
+#define PWM35HLD (*(unsigned char volatile xdata *)0xfc3d)
+#define PWM36T1 (*(unsigned int volatile xdata *)0xfc40)
+#define PWM36T1H (*(unsigned char volatile xdata *)0xfc40)
+#define PWM36T1L (*(unsigned char volatile xdata *)0xfc41)
+#define PWM36T2 (*(unsigned int volatile xdata *)0xfc42)
+#define PWM36T2H (*(unsigned char volatile xdata *)0xfc42)
+#define PWM36T2L (*(unsigned char volatile xdata *)0xfc43)
+#define PWM36CR (*(unsigned char volatile xdata *)0xfc44)
+#define PWM36HLD (*(unsigned char volatile xdata *)0xfc45)
+#define PWM37T1 (*(unsigned int volatile xdata *)0xfc48)
+#define PWM37T1H (*(unsigned char volatile xdata *)0xfc48)
+#define PWM37T1L (*(unsigned char volatile xdata *)0xfc49)
+#define PWM37T2 (*(unsigned int volatile xdata *)0xfc4a)
+#define PWM37T2H (*(unsigned char volatile xdata *)0xfc4a)
+#define PWM37T2L (*(unsigned char volatile xdata *)0xfc4b)
+#define PWM37CR (*(unsigned char volatile xdata *)0xfc4c)
+#define PWM37HLD (*(unsigned char volatile xdata *)0xfc4d)
+#define PWM4C (*(unsigned int volatile xdata *)0xfc50)
+#define PWM4CH (*(unsigned char volatile xdata *)0xfc50)
+#define PWM4CL (*(unsigned char volatile xdata *)0xfc51)
+#define PWM4CKS (*(unsigned char volatile xdata *)0xfc52)
+#define PWM4TADC (*(unsigned int volatile xdata *)0xfc53)
+#define PWM4TADCH (*(unsigned char volatile xdata *)0xfc53)
+#define PWM4TADCL (*(unsigned char volatile xdata *)0xfc54)
+#define PWM4IF (*(unsigned char volatile xdata *)0xfc55)
+#define PWM4FDCR (*(unsigned char volatile xdata *)0xfc56)
+#define PWM40T1 (*(unsigned int volatile xdata *)0xfc60)
+#define PWM40T1H (*(unsigned char volatile xdata *)0xfc60)
+#define PWM40T1L (*(unsigned char volatile xdata *)0xfc61)
+#define PWM40T2 (*(unsigned int volatile xdata *)0xfc62)
+#define PWM40T2H (*(unsigned char volatile xdata *)0xfc62)
+#define PWM40T2L (*(unsigned char volatile xdata *)0xfc63)
+#define PWM40CR (*(unsigned char volatile xdata *)0xfc64)
+#define PWM40HLD (*(unsigned char volatile xdata *)0xfc65)
+#define PWM41T1 (*(unsigned int volatile xdata *)0xfc68)
+#define PWM41T1H (*(unsigned char volatile xdata *)0xfc68)
+#define PWM41T1L (*(unsigned char volatile xdata *)0xfc69)
+#define PWM41T2 (*(unsigned int volatile xdata *)0xfc6a)
+#define PWM41T2H (*(unsigned char volatile xdata *)0xfc6a)
+#define PWM41T2L (*(unsigned char volatile xdata *)0xfc6b)
+#define PWM41CR (*(unsigned char volatile xdata *)0xfc6c)
+#define PWM41HLD (*(unsigned char volatile xdata *)0xfc6d)
+#define PWM42T1 (*(unsigned int volatile xdata *)0xfc70)
+#define PWM42T1H (*(unsigned char volatile xdata *)0xfc70)
+#define PWM42T1L (*(unsigned char volatile xdata *)0xfc71)
+#define PWM42T2 (*(unsigned int volatile xdata *)0xfc72)
+#define PWM42T2H (*(unsigned char volatile xdata *)0xfc72)
+#define PWM42T2L (*(unsigned char volatile xdata *)0xfc73)
+#define PWM42CR (*(unsigned char volatile xdata *)0xfc74)
+#define PWM42HLD (*(unsigned char volatile xdata *)0xfc75)
+#define PWM43T1 (*(unsigned int volatile xdata *)0xfc78)
+#define PWM43T1H (*(unsigned char volatile xdata *)0xfc78)
+#define PWM43T1L (*(unsigned char volatile xdata *)0xfc79)
+#define PWM43T2 (*(unsigned int volatile xdata *)0xfc7a)
+#define PWM43T2H (*(unsigned char volatile xdata *)0xfc7a)
+#define PWM43T2L (*(unsigned char volatile xdata *)0xfc7b)
+#define PWM43CR (*(unsigned char volatile xdata *)0xfc7c)
+#define PWM43HLD (*(unsigned char volatile xdata *)0xfc7d)
+#define PWM44T1 (*(unsigned int volatile xdata *)0xfc80)
+#define PWM44T1H (*(unsigned char volatile xdata *)0xfc80)
+#define PWM44T1L (*(unsigned char volatile xdata *)0xfc81)
+#define PWM44T2 (*(unsigned int volatile xdata *)0xfc82)
+#define PWM44T2H (*(unsigned char volatile xdata *)0xfc82)
+#define PWM44T2L (*(unsigned char volatile xdata *)0xfc83)
+#define PWM44CR (*(unsigned char volatile xdata *)0xfc84)
+#define PWM44HLD (*(unsigned char volatile xdata *)0xfc85)
+#define PWM45T1 (*(unsigned int volatile xdata *)0xfc88)
+#define PWM45T1H (*(unsigned char volatile xdata *)0xfc88)
+#define PWM45T1L (*(unsigned char volatile xdata *)0xfc89)
+#define PWM45T2 (*(unsigned int volatile xdata *)0xfc8a)
+#define PWM45T2H (*(unsigned char volatile xdata *)0xfc8a)
+#define PWM45T2L (*(unsigned char volatile xdata *)0xfc8b)
+#define PWM45CR (*(unsigned char volatile xdata *)0xfc8c)
+#define PWM45HLD (*(unsigned char volatile xdata *)0xfc8d)
+#define PWM46T1 (*(unsigned int volatile xdata *)0xfc90)
+#define PWM46T1H (*(unsigned char volatile xdata *)0xfc90)
+#define PWM46T1L (*(unsigned char volatile xdata *)0xfc91)
+#define PWM46T2 (*(unsigned int volatile xdata *)0xfc92)
+#define PWM46T2H (*(unsigned char volatile xdata *)0xfc92)
+#define PWM46T2L (*(unsigned char volatile xdata *)0xfc93)
+#define PWM46CR (*(unsigned char volatile xdata *)0xfc94)
+#define PWM46HLD (*(unsigned char volatile xdata *)0xfc95)
+#define PWM47T1 (*(unsigned int volatile xdata *)0xfc98)
+#define PWM47T1H (*(unsigned char volatile xdata *)0xfc98)
+#define PWM47T1L (*(unsigned char volatile xdata *)0xfc99)
+#define PWM47T2 (*(unsigned int volatile xdata *)0xfc9a)
+#define PWM47T2H (*(unsigned char volatile xdata *)0xfc9a)
+#define PWM47T2L (*(unsigned char volatile xdata *)0xfc9b)
+#define PWM47CR (*(unsigned char volatile xdata *)0xfc9c)
+#define PWM47HLD (*(unsigned char volatile xdata *)0xfc9d)
+#define PWM5C (*(unsigned int volatile xdata *)0xfca0)
+#define PWM5CH (*(unsigned char volatile xdata *)0xfca0)
+#define PWM5CL (*(unsigned char volatile xdata *)0xfca1)
+#define PWM5CKS (*(unsigned char volatile xdata *)0xfca2)
+#define PWM5IF (*(unsigned char volatile xdata *)0xfca5)
+#define PWM5FDCR (*(unsigned char volatile xdata *)0xfca6)
+#define PWM50T1 (*(unsigned int volatile xdata *)0xfcb0)
+#define PWM50T1H (*(unsigned char volatile xdata *)0xfcb0)
+#define PWM50T1L (*(unsigned char volatile xdata *)0xfcb1)
+#define PWM50T2 (*(unsigned int volatile xdata *)0xfcb2)
+#define PWM50T2H (*(unsigned char volatile xdata *)0xfcb2)
+#define PWM50T2L (*(unsigned char volatile xdata *)0xfcb3)
+#define PWM50CR (*(unsigned char volatile xdata *)0xfcb4)
+#define PWM50HLD (*(unsigned char volatile xdata *)0xfcb5)
+#define PWM51T1 (*(unsigned int volatile xdata *)0xfcb8)
+#define PWM51T1H (*(unsigned char volatile xdata *)0xfcb8)
+#define PWM51T1L (*(unsigned char volatile xdata *)0xfcb9)
+#define PWM51T2 (*(unsigned int volatile xdata *)0xfcba)
+#define PWM51T2H (*(unsigned char volatile xdata *)0xfcba)
+#define PWM51T2L (*(unsigned char volatile xdata *)0xfcbb)
+#define PWM51CR (*(unsigned char volatile xdata *)0xfcbc)
+#define PWM51HLD (*(unsigned char volatile xdata *)0xfcbd)
+#define PWM52T1 (*(unsigned int volatile xdata *)0xfcc0)
+#define PWM52T1H (*(unsigned char volatile xdata *)0xfcc0)
+#define PWM52T1L (*(unsigned char volatile xdata *)0xfcc1)
+#define PWM52T2 (*(unsigned int volatile xdata *)0xfcc2)
+#define PWM52T2H (*(unsigned char volatile xdata *)0xfcc2)
+#define PWM52T2L (*(unsigned char volatile xdata *)0xfcc3)
+#define PWM52CR (*(unsigned char volatile xdata *)0xfcc4)
+#define PWM52HLD (*(unsigned char volatile xdata *)0xfcc5)
+#define PWM53T1 (*(unsigned int volatile xdata *)0xfcc8)
+#define PWM53T1H (*(unsigned char volatile xdata *)0xfcc8)
+#define PWM53T1L (*(unsigned char volatile xdata *)0xfcc9)
+#define PWM53T2 (*(unsigned int volatile xdata *)0xfcca)
+#define PWM53T2H (*(unsigned char volatile xdata *)0xfcca)
+#define PWM53T2L (*(unsigned char volatile xdata *)0xfccb)
+#define PWM53CR (*(unsigned char volatile xdata *)0xfccc)
+#define PWM53HLD (*(unsigned char volatile xdata *)0xfccd)
+#define PWM54T1 (*(unsigned int volatile xdata *)0xfcd0)
+#define PWM54T1H (*(unsigned char volatile xdata *)0xfcd0)
+#define PWM54T1L (*(unsigned char volatile xdata *)0xfcd1)
+#define PWM54T2 (*(unsigned int volatile xdata *)0xfcd2)
+#define PWM54T2H (*(unsigned char volatile xdata *)0xfcd2)
+#define PWM54T2L (*(unsigned char volatile xdata *)0xfcd3)
+#define PWM54CR (*(unsigned char volatile xdata *)0xfcd4)
+#define PWM54HLD (*(unsigned char volatile xdata *)0xfcd5)
+#define PWM55T1 (*(unsigned int volatile xdata *)0xfcd8)
+#define PWM55T1H (*(unsigned char volatile xdata *)0xfcd8)
+#define PWM55T1L (*(unsigned char volatile xdata *)0xfcd9)
+#define PWM55T2 (*(unsigned int volatile xdata *)0xfcda)
+#define PWM55T2H (*(unsigned char volatile xdata *)0xfcda)
+#define PWM55T2L (*(unsigned char volatile xdata *)0xfcdb)
+#define PWM55CR (*(unsigned char volatile xdata *)0xfcdc)
+#define PWM55HLD (*(unsigned char volatile xdata *)0xfcdd)
+#define PWM56T1 (*(unsigned int volatile xdata *)0xfce0)
+#define PWM56T1H (*(unsigned char volatile xdata *)0xfce0)
+#define PWM56T1L (*(unsigned char volatile xdata *)0xfce1)
+#define PWM56T2 (*(unsigned int volatile xdata *)0xfce2)
+#define PWM56T2H (*(unsigned char volatile xdata *)0xfce2)
+#define PWM56T2L (*(unsigned char volatile xdata *)0xfce3)
+#define PWM56CR (*(unsigned char volatile xdata *)0xfce4)
+#define PWM56HLD (*(unsigned char volatile xdata *)0xfce5)
+#define PWM57T1 (*(unsigned int volatile xdata *)0xfce8)
+#define PWM57T1H (*(unsigned char volatile xdata *)0xfce8)
+#define PWM57T1L (*(unsigned char volatile xdata *)0xfce9)
+#define PWM57T2 (*(unsigned int volatile xdata *)0xfcea)
+#define PWM57T2H (*(unsigned char volatile xdata *)0xfcea)
+#define PWM57T2L (*(unsigned char volatile xdata *)0xfceb)
+#define PWM57CR (*(unsigned char volatile xdata *)0xfcec)
+#define PWM57HLD (*(unsigned char volatile xdata *)0xfced)
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMSET = 0xF1H; ENGLBSET PWMRST ENPWM5 ENPWM4 ENPWM3 ENPWM2 ENPWM1 ENPWM0 0000,0000 /* ǿPWMȫüĴ */
+#define PWM15_SET_Uniform() PWMSET |= 0x80 //16PWMͳһ÷ʽ
+#define PWM15_SET_Independent() PWMSET &= ~0x80 //06PWMøԶ÷ʽ
+
+#define PWM15_Reset() PWMSET |= 0x40 //1λPWMXFRĴSFR
+
+#define PWM15_PWM5_Enable() PWMSET |= 0x20 //1ʹPWM5 PWM50~PWM54
+#define PWM15_PWM5_Disable() PWMSET &= ~0x20 //0رPWM5
+
+#define PWM15_PWM4_Enable() PWMSET |= 0x10 //1ʹPWM4 PWM40~PWM47
+#define PWM15_PWM4_Disable() PWMSET &= ~0x10 //0رPWM4
+
+#define PWM15_PWM3_Enable() PWMSET |= 0x08 //1ʹPWM3 PWM30~PWM37
+#define PWM15_PWM3_Disable() PWMSET &= ~0x08 //0رPWM3
+
+#define PWM15_PWM2_Enable() PWMSET |= 0x04 //1ʹPWM2 PWM20~PWM27
+#define PWM15_PWM2_Disable() PWMSET &= ~0x04 //0رPWM2
+
+#define PWM15_PWM1_Enable() PWMSET |= 0x02 //1ʹPWM1 PWM10~PWM17
+#define PWM15_PWM1_Disable() PWMSET &= ~0x02 //0رPWM1
+
+#define PWM15_PWM0_Enable() PWMSET |= 0x01 //1ʹPWM0 PWM00~PWM07
+#define PWM15_PWM0_Disable() PWMSET &= ~0x01 //0رPWM0
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMCFG01= 0xF6H; PWM1CBIF EPWM1CBI FLTPS0 PWM1CEN PWM0CBIF EPWM0CBI ENPWM0TA PWM0CEN 0000,0000 /* ǿPWMüĴ */
+//sfr PWMCFG23= 0xF7H; PWM3CBIF EPWM3CBI FLTPS1 PWM3CEN PWM2CBIF EPWM2CBI ENPWM2TA PWM2CEN 0000,0000 /* ǿPWMüĴ */
+//sfr PWMCFG45= 0xFEH; PWM5CBIF EPWM5CBI FLTPS2 PWM5CEN PWM4CBIF EPWM4CBI ENPWM4TA PWM4CEN 0000,0000 /* ǿPWMüĴ */
+#define PWM1CBIF 0x80
+#define PWM0CBIF 0x08
+#define FLTPSn 0x20
+
+#define PWM15_Counter1Int_Enable() PWMCFG01 |= 0x40 //1ʹܼж
+#define PWM15_Counter1Int_Disable() PWMCFG01 &= ~0x40 //0رռж
+#define PWM15_Counter1_Enable() PWMCFG01 |= 0x10 //1ʹܼ
+#define PWM15_Counter1_Disable() PWMCFG01 &= ~0x10 //0رռ
+#define PWM15_Counter0Int_Enable() PWMCFG01 |= 0x04 //1ʹܼж
+#define PWM15_Counter0Int_Disable() PWMCFG01 &= ~0x04 //0رռж
+#define PWM15_Counter0_Enable() PWMCFG01 |= 0x01 //1ʹܼ
+#define PWM15_Counter0_Disable() PWMCFG01 &= ~0x01 //0رռ
+#define PWM15_PWM0_ADC_Enable() PWMCFG01 |= 0x02 //1PWMADC
+#define PWM15_PWM0_ADC_Disable() PWMCFG01 &= ~0x02 //0PWMADC
+
+#define PWM15_Counter3Int_Enable() PWMCFG23 |= 0x40 //1ʹܼж
+#define PWM15_Counter3Int_Disable() PWMCFG23 &= ~0x40 //0رռж
+#define PWM15_Counter3_Enable() PWMCFG23 |= 0x10 //1ʹܼ
+#define PWM15_Counter3_Disable() PWMCFG23 &= ~0x10 //0رռ
+#define PWM15_Counter2Int_Enable() PWMCFG23 |= 0x04 //1ʹܼж
+#define PWM15_Counter2Int_Disable() PWMCFG23 &= ~0x04 //0رռж
+#define PWM15_Counter2_Enable() PWMCFG23 |= 0x01 //1ʹܼ
+#define PWM15_Counter2_Disable() PWMCFG23 &= ~0x01 //0رռ
+#define PWM15_PWM2_ADC_Enable() PWMCFG23 |= 0x02 //1PWMADC
+#define PWM15_PWM2_ADC_Disable() PWMCFG23 &= ~0x02 //0PWMADC
+
+#define PWM15_Counter5Int_Enable() PWMCFG45 |= 0x40 //1ʹܼж
+#define PWM15_Counter5Int_Disable() PWMCFG45 &= ~0x40 //0رռж
+#define PWM15_Counter5_Enable() PWMCFG45 |= 0x10 //1ʹܼ
+#define PWM15_Counter5_Disable() PWMCFG45 &= ~0x10 //0رռ
+#define PWM15_Counter4Int_Enable() PWMCFG45 |= 0x04 //1ʹܼж
+#define PWM15_Counter4Int_Disable() PWMCFG45 &= ~0x04 //0رռж
+#define PWM15_Counter4_Enable() PWMCFG45 |= 0x01 //1ʹܼ
+#define PWM15_Counter4_Disable() PWMCFG45 &= ~0x01 //0رռ
+#define PWM15_PWM4_ADC_Enable() PWMCFG45 |= 0x02 //1PWMADC
+#define PWM15_PWM4_ADC_Disable() PWMCFG45 &= ~0x02 //0PWMADC
+
+/* PWMnIF */
+#define C7IF = (1<<7)
+#define C6IF = (1<<6)
+#define C5IF = (1<<5)
+#define C4IF = (1<<4)
+#define C3IF = (1<<3)
+#define C2IF = (1<<2)
+#define C1IF = (1<<1)
+#define C0IF = 1
+
+/* PWMnFDCR */
+#define INVCMP = (1<<7)
+#define INVIO = (1<<6)
+#define ENFD = (1<<5)
+#define FLTFLIO = (1<<4)
+#define EFDI = (1<<3)
+#define FDCMP = (1<<2)
+#define FDIO = (1<<1)
+#define FDIF = 1
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWM0CKS = 0xFF02H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */
+//sfr PWM1CKS = 0xFF52H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */
+//sfr PWM2CKS = 0xFFA2H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */
+//sfr PWM3CKS = 0xFC02H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */
+//sfr PWM4CKS = 0xFC52H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */
+//sfr PWM5CKS = 0xFCA2H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ǿPWMʱѡ */
+#define PWM0_PS_Clock() PWM0CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ
+#define PWM0_T2_Clock() PWM0CKS |= 0x10 //1PWMnʱԴΪʱ2
+#define PWM0_PS_Set(n) PWM0CKS = (PWM0CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1)
+#define PWM1_PS_Clock() PWM1CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ
+#define PWM1_T2_Clock() PWM1CKS |= 0x10 //1PWMnʱԴΪʱ2
+#define PWM1_PS_Set(n) PWM1CKS = (PWM1CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1)
+#define PWM2_PS_Clock() PWM2CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ
+#define PWM2_T2_Clock() PWM2CKS |= 0x10 //1PWMnʱԴΪʱ2
+#define PWM2_PS_Set(n) PWM2CKS = (PWM2CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1)
+#define PWM3_PS_Clock() PWM3CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ
+#define PWM3_T2_Clock() PWM3CKS |= 0x10 //1PWMnʱԴΪʱ2
+#define PWM3_PS_Set(n) PWM3CKS = (PWM3CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1)
+#define PWM4_PS_Clock() PWM4CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ
+#define PWM4_T2_Clock() PWM4CKS |= 0x10 //1PWMnʱԴΪʱ2
+#define PWM4_PS_Set(n) PWM4CKS = (PWM4CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1)
+#define PWM5_PS_Clock() PWM5CKS &= ~0x10 //0PWMnʱԴΪϵͳʱӷƵʱ
+#define PWM5_T2_Clock() PWM5CKS |= 0x10 //1PWMnʱԴΪʱ2
+#define PWM5_PS_Set(n) PWM5CKS = (PWM5CKS & ~0x0F) | (n & 0x0F) //ϵͳʱԤƵãSYSclk / (PWM_PS+1)
+
+/* PWMnTADC */
+#define PWM15_PWM0TADC(n) PWM0TADC = (n & 0x7fff) //PWMADCʱ
+#define PWM15_PWM2TADC(n) PWM2TADC = (n & 0x7fff) //PWMADCʱ
+#define PWM15_PWM4TADC(n) PWM4TADC = (n & 0x7fff) //PWMADCʱ
+
+/* PWMnTADC */
+#define PWM15_PWM0TADC(n) PWM0TADC = (n & 0x7fff) //PWMADCʱ
+
+
+/* BIT Registers */
+/* PSW */
+sbit CY = PSW^7;
+sbit AC = PSW^6;
+sbit F0 = PSW^5;
+sbit RS1 = PSW^4;
+sbit RS0 = PSW^3;
+sbit OV = PSW^2;
+sbit F1 = PSW^1;
+sbit P = PSW^0;
+
+/* TCON */
+sbit TF1 = TCON^7; //ʱ1жϱ־λ
+sbit TR1 = TCON^6; //ʱ1пλ
+sbit TF0 = TCON^5; //ʱ0жϱ־λ
+sbit TR0 = TCON^4; //ʱ0пλ
+sbit IE1 = TCON^3; //ж1־λ
+sbit IT1 = TCON^2; //ж1źŷʽλ1½жϣ0½жϡ
+sbit IE0 = TCON^1; //ж0־λ
+sbit IT0 = TCON^0; //ж0źŷʽλ1½жϣ0½жϡ
+
+/* P0 */
+sbit P00 = P0^0;
+sbit P01 = P0^1;
+sbit P02 = P0^2;
+sbit P03 = P0^3;
+sbit P04 = P0^4;
+sbit P05 = P0^5;
+sbit P06 = P0^6;
+sbit P07 = P0^7;
+
+/* P1 */
+sbit P10 = P1^0;
+sbit P11 = P1^1;
+sbit P12 = P1^2;
+sbit P13 = P1^3;
+sbit P14 = P1^4;
+sbit P15 = P1^5;
+sbit P16 = P1^6;
+sbit P17 = P1^7;
+
+sbit RXD2 = P1^0;
+sbit TXD2 = P1^1;
+sbit CCP1 = P1^0;
+sbit CCP0 = P1^1;
+sbit SPI_SS = P1^2;
+sbit SPI_MOSI = P1^3;
+sbit SPI_MISO = P1^4;
+sbit SPI_SCLK = P1^5;
+
+sbit SPI_SS_2 = P2^2;
+sbit SPI_MOSI_2 = P2^3;
+sbit SPI_MISO_2 = P2^4;
+sbit SPI_SCLK_2 = P2^5;
+
+sbit SPI_SS_3 = P5^4;
+sbit SPI_MOSI_3 = P4^0;
+sbit SPI_MISO_3 = P4^1;
+sbit SPI_SCLK_3 = P4^3;
+
+sbit SPI_SS_4 = P3^5;
+sbit SPI_MOSI_4 = P3^4;
+sbit SPI_MISO_4 = P3^3;
+sbit SPI_SCLK_4 = P3^2;
+
+/* P2 */
+sbit P20 = P2^0;
+sbit P21 = P2^1;
+sbit P22 = P2^2;
+sbit P23 = P2^3;
+sbit P24 = P2^4;
+sbit P25 = P2^5;
+sbit P26 = P2^6;
+sbit P27 = P2^7;
+
+/* P3 */
+sbit P30 = P3^0;
+sbit P31 = P3^1;
+sbit P32 = P3^2;
+sbit P33 = P3^3;
+sbit P34 = P3^4;
+sbit P35 = P3^5;
+sbit P36 = P3^6;
+sbit P37 = P3^7;
+
+sbit RXD = P3^0;
+sbit TXD = P3^1;
+sbit INT0 = P3^2;
+sbit INT1 = P3^3;
+sbit T0 = P3^4;
+sbit T1 = P3^5;
+sbit WR = P3^6;
+sbit RD = P3^7;
+
+sbit INT2 = P3^6;
+sbit INT3 = P3^7;
+sbit INT4 = P3^0;
+sbit CCP2 = P3^7;
+
+sbit CLKOUT0 = P3^5;
+sbit CLKOUT1 = P3^4;
+
+/* P4 */
+sbit P40 = P4^0;
+sbit P41 = P4^1;
+sbit P42 = P4^2;
+sbit P43 = P4^3;
+sbit P44 = P4^4;
+sbit P45 = P4^5;
+sbit P46 = P4^6;
+sbit P47 = P4^7;
+
+/* P5 */
+sbit P50 = P5^0;
+sbit P51 = P5^1;
+sbit P52 = P5^2;
+sbit P53 = P5^3;
+sbit P54 = P5^4;
+sbit P55 = P5^5;
+sbit P56 = P5^6;
+sbit P57 = P5^7;
+
+/* P6 */
+sbit P60 = P6^0;
+sbit P61 = P6^1;
+sbit P62 = P6^2;
+sbit P63 = P6^3;
+sbit P64 = P6^4;
+sbit P65 = P6^5;
+sbit P66 = P6^6;
+sbit P67 = P6^7;
+
+/* P7 */
+sbit P70 = P7^0;
+sbit P71 = P7^1;
+sbit P72 = P7^2;
+sbit P73 = P7^3;
+sbit P74 = P7^4;
+sbit P75 = P7^5;
+sbit P76 = P7^6;
+sbit P77 = P7^7;
+
+
+/* SCON */
+sbit SM0 = SCON^7; //SM0/FE SM0 SM1 = 00 ~ 11: ʽ0~3
+sbit SM1 = SCON^6; //
+sbit SM2 = SCON^5; //ͨѶ
+sbit REN = SCON^4; //
+sbit TB8 = SCON^3; //ݵ8λ
+sbit RB8 = SCON^2; //ݵ8λ
+sbit TI = SCON^1; //жϱ־λ
+sbit RI = SCON^0; //жϱ־λ
+
+/* IE */
+sbit EA = IE^7; //жܿλ
+sbit ELVD = IE^6; //ѹжλ
+sbit EADC = IE^5; //ADC ж λ
+sbit ES = IE^4; //ж λ
+sbit ET1 = IE^3; //ʱж1λ
+sbit EX1 = IE^2; //ⲿж1λ
+sbit ET0 = IE^1; //ʱж0λ
+sbit EX0 = IE^0; //ⲿж0λ
+
+sbit ACC0 = ACC^0;
+sbit ACC1 = ACC^1;
+sbit ACC2 = ACC^2;
+sbit ACC3 = ACC^3;
+sbit ACC4 = ACC^4;
+sbit ACC5 = ACC^5;
+sbit ACC6 = ACC^6;
+sbit ACC7 = ACC^7;
+
+sbit B0 = B^0;
+sbit B1 = B^1;
+sbit B2 = B^2;
+sbit B3 = B^3;
+sbit B4 = B^4;
+sbit B5 = B^5;
+sbit B6 = B^6;
+sbit B7 = B^7;
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IE2 = 0xAF; ETKSUI ET4 ET3 ES4 ES3 ET2 ESPI ES2 x000,0000B //Auxiliary Interrupt
+#define SPI_INT_ENABLE() IE2 |= 2 /* SPIж */
+#define SPI_INT_DISABLE() IE2 &= ~2 /* SPIж */
+#define UART2_INT_ENABLE() IE2 |= 1 /* 2ж */
+#define UART2_INT_DISABLE() IE2 &= ~1 /* 2ж */
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IP2 = 0xB5; // PPWM2FD PI2C PCMP PX4 PPWM0FD PPWM0 PSPI PS2 0000,0000
+#define PUSB 0x80
+#define PPWM2FD 0x80
+#define PTKSU 0x80
+#define PI2C 0x40
+#define PCMP 0x20
+#define PX4 0x10
+#define PPWM0FD 0x08
+#define PPWM0 0x04
+#define PSPI 0x02
+#define PS2 0x01
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IP2H = 0xB6; // PPWM2FDH PI2CH PCMPH PX4H PPWM0FDH PPWM0H PSPIH PS2H 0000,0000
+#define PUSBH 0x80
+#define PPWM2FDH 0x80
+#define PTKSUH 0x80
+#define PI2CH 0x40
+#define PCMPH 0x20
+#define PX4H 0x10
+#define PPWM0FDH 0x08
+#define PPWM0H 0x04
+#define PSPIH 0x02
+#define PS2H 0x01
+
+//2жȼ
+#define UART2_Priority(n) do{if(n == 0) IP2H &= ~PS2H, IP2 &= ~PS2; \
+ if(n == 1) IP2H &= ~PS2H, IP2 |= PS2; \
+ if(n == 2) IP2H |= PS2H, IP2 &= ~PS2; \
+ if(n == 3) IP2H |= PS2H, IP2 |= PS2; \
+ }while(0)
+//SPIжȼ
+#define SPI_Priority(n) do{if(n == 0) IP2H &= ~PSPIH, IP2 &= ~PSPI; \
+ if(n == 1) IP2H &= ~PSPIH, IP2 |= PSPI; \
+ if(n == 2) IP2H |= PSPIH, IP2 &= ~PSPI; \
+ if(n == 3) IP2H |= PSPIH, IP2 |= PSPI; \
+ }while(0)
+//ⲿж4жȼ
+#define INT4_Priority(n) do{if(n == 0) IP2H &= ~PX4H, IP2 &= ~PX4; \
+ if(n == 1) IP2H &= ~PX4H, IP2 |= PX4; \
+ if(n == 2) IP2H |= PX4H, IP2 &= ~PX4; \
+ if(n == 3) IP2H |= PX4H, IP2 |= PX4; \
+ }while(0)
+//Ƚжȼ
+#define CMP_Priority(n) do{if(n == 0) IP2H &= ~PCMPH, IP2 &= ~PCMP; \
+ if(n == 1) IP2H &= ~PCMPH, IP2 |= PCMP; \
+ if(n == 2) IP2H |= PCMPH, IP2 &= ~PCMP; \
+ if(n == 3) IP2H |= PCMPH, IP2 |= PCMP; \
+ }while(0)
+//I2Cжȼ
+#define I2C_Priority(n) do{if(n == 0) IP2H &= ~PI2CH, IP2 &= ~PI2C; \
+ if(n == 1) IP2H &= ~PI2CH, IP2 |= PI2C; \
+ if(n == 2) IP2H |= PI2CH, IP2 &= ~PI2C; \
+ if(n == 3) IP2H |= PI2CH, IP2 |= PI2C; \
+ }while(0)
+//ǿPWM0жȼ
+#define PWM0_Priority(n) do{if(n == 0) IP2H &= ~PPWM0H, IP2 &= ~PPWM0; \
+ if(n == 1) IP2H &= ~PPWM0H, IP2 |= PPWM0; \
+ if(n == 2) IP2H |= PPWM0H, IP2 &= ~PPWM0; \
+ if(n == 3) IP2H |= PPWM0H, IP2 |= PPWM0; \
+ }while(0)
+//ǿPWM0쳣жȼ
+#define PWM0FD_Priority(n) do{if(n == 0) IP2H &= ~PPWM0FDH, IP2 &= ~PPWM0FD; \
+ if(n == 1) IP2H &= ~PPWM0FDH, IP2 |= PPWM0FD; \
+ if(n == 2) IP2H |= PPWM0FDH, IP2 &= ~PPWM0FD; \
+ if(n == 3) IP2H |= PPWM0FDH, IP2 |= PPWM0FD; \
+ }while(0)
+//ǿPWM2쳣жȼ
+#define PWM2FD_Priority(n) do{if(n == 0) IP2H &= ~PPWM2FDH, IP2 &= ~PPWM2FD; \
+ if(n == 1) IP2H &= ~PPWM2FDH, IP2 |= PPWM2FD; \
+ if(n == 2) IP2H |= PPWM2FDH, IP2 &= ~PPWM2FD; \
+ if(n == 3) IP2H |= PPWM2FDH, IP2 |= PPWM2FD; \
+ }while(0)
+//жȼ
+#define PTKSU_Priority(n) do{if(n == 0) IP2H &= ~PTKSUH, IP2 &= ~PTKSU; \
+ if(n == 1) IP2H &= ~PTKSUH, IP2 |= PTKSU; \
+ if(n == 2) IP2H |= PTKSUH, IP2 &= ~PTKSU; \
+ if(n == 3) IP2H |= PTKSUH, IP2 |= PTKSU; \
+ }while(0)
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IP3 = 0xDF; // PPWM4FD PPWM5 PPWM4 PPWM3 PPWM2 PPWM1 PS4 PS3 0000,0000
+#define PPWM4FD 0x80
+#define PPWM5 0x40
+#define PPWM4 0x20
+#define PPWM3 0x10
+#define PPWM2 0x08
+#define PPWM1 0x04
+#define PRTC 0x04
+#define PS4 0x02
+#define PS3 0x01
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IP3H = 0xEE; // PPWM4FDH PPWM5H PPWM4H PPWM3H PPWM2H PPWM1H PS4H PS3H 0000,0000
+#define PPWM4FDH 0x80
+#define PPWM5H 0x40
+#define PPWM4H 0x20
+#define PPWM3H 0x10
+#define PPWM2H 0x08
+#define PPWM1H 0x04
+#define PRTCH 0x04
+#define PS4H 0x02
+#define PS3H 0x01
+
+#ifdef STC8Hxx
+
+//ǿPWM1жȼ
+#define PWM1_Priority(n) do{if(n == 0) IP2H &= ~PPWM1H, IP2 &= ~PPWM1; \
+ if(n == 1) IP2H &= ~PPWM1H, IP2 |= PPWM1; \
+ if(n == 2) IP2H |= PPWM1H, IP2 &= ~PPWM1; \
+ if(n == 3) IP2H |= PPWM1H, IP2 |= PPWM1; \
+ }while(0)
+//ǿPWM2жȼ
+#define PWM2_Priority(n) do{if(n == 0) IP2H &= ~PPWM2H, IP2 &= ~PPWM2; \
+ if(n == 1) IP2H &= ~PPWM2H, IP2 |= PPWM2; \
+ if(n == 2) IP2H |= PPWM2H, IP2 &= ~PPWM2; \
+ if(n == 3) IP2H |= PPWM2H, IP2 |= PPWM2; \
+ }while(0)
+//USBжȼ
+#define USB_Priority(n) do{if(n == 0) IP2H &= ~PUSBH, IP2 &= ~PUSB; \
+ if(n == 1) IP2H &= ~PUSBH, IP2 |= PUSB; \
+ if(n == 2) IP2H |= PUSBH, IP2 &= ~PUSB; \
+ if(n == 3) IP2H |= PUSBH, IP2 |= PUSB; \
+ }while(0)
+//RTCжȼ
+#define RTC_Priority(n) do{if(n == 0) IP3H &= ~PRTCH, IP3 &= ~PRTC; \
+ if(n == 1) IP3H &= ~PRTCH, IP3 |= PRTC; \
+ if(n == 2) IP3H |= PRTCH, IP3 &= ~PRTC; \
+ if(n == 3) IP3H |= PRTCH, IP3 |= PRTC; \
+ }while(0)
+#else
+
+//ǿPWM1жȼ
+#define PWM1_Priority(n) do{if(n == 0) IP3H &= ~PPWM1H, IP3 &= ~PPWM1; \
+ if(n == 1) IP3H &= ~PPWM1H, IP3 |= PPWM1; \
+ if(n == 2) IP3H |= PPWM1H, IP3 &= ~PPWM1; \
+ if(n == 3) IP3H |= PPWM1H, IP3 |= PPWM1; \
+ }while(0)
+//ǿPWM2жȼ
+#define PWM2_Priority(n) do{if(n == 0) IP3H &= ~PPWM2H, IP3 &= ~PPWM2; \
+ if(n == 1) IP3H &= ~PPWM2H, IP3 |= PPWM2; \
+ if(n == 2) IP3H |= PPWM2H, IP3 &= ~PPWM2; \
+ if(n == 3) IP3H |= PPWM2H, IP3 |= PPWM2; \
+ }while(0)
+
+#endif
+
+//ǿPWM3жȼ
+#define PWM3_Priority(n) do{if(n == 0) IP3H &= ~PPWM3H, IP3 &= ~PPWM3; \
+ if(n == 1) IP3H &= ~PPWM3H, IP3 |= PPWM3; \
+ if(n == 2) IP3H |= PPWM3H, IP3 &= ~PPWM3; \
+ if(n == 3) IP3H |= PPWM3H, IP3 |= PPWM3; \
+ }while(0)
+//ǿPWM4жȼ
+#define PWM4_Priority(n) do{if(n == 0) IP3H &= ~PPWM4H, IP3 &= ~PPWM4; \
+ if(n == 1) IP3H &= ~PPWM4H, IP3 |= PPWM4; \
+ if(n == 2) IP3H |= PPWM4H, IP3 &= ~PPWM4; \
+ if(n == 3) IP3H |= PPWM4H, IP3 |= PPWM4; \
+ }while(0)
+//ǿPWM5жȼ
+#define PWM5_Priority(n) do{if(n == 0) IP3H &= ~PPWM5H, IP3 &= ~PPWM5; \
+ if(n == 1) IP3H &= ~PPWM5H, IP3 |= PPWM5; \
+ if(n == 2) IP3H |= PPWM5H, IP3 &= ~PPWM5; \
+ if(n == 3) IP3H |= PPWM5H, IP3 |= PPWM5; \
+ }while(0)
+//ǿPWM4쳣жȼ
+#define PWM4FD_Priority(n) do{if(n == 0) IP3H &= ~PPWM4FDH, IP3 &= ~PPWM4FD; \
+ if(n == 1) IP3H &= ~PPWM4FDH, IP3 |= PPWM4FD; \
+ if(n == 2) IP3H |= PPWM4FDH, IP3 &= ~PPWM4FD; \
+ if(n == 3) IP3H |= PPWM4FDH, IP3 |= PPWM4FD; \
+ }while(0)
+//3жȼ
+#define UART3_Priority(n) do{if(n == 0) IP3H &= ~PS3H, IP3 &= ~PS3; \
+ if(n == 1) IP3H &= ~PS3H, IP3 |= PS3; \
+ if(n == 2) IP3H |= PS3H, IP3 &= ~PS3; \
+ if(n == 3) IP3H |= PS3H, IP3 |= PS3; \
+ }while(0)
+//4жȼ
+#define UART4_Priority(n) do{if(n == 0) IP3H &= ~PS4H, IP3 &= ~PS4; \
+ if(n == 1) IP3H &= ~PS4H, IP3 |= PS4; \
+ if(n == 2) IP3H |= PS4H, IP3 &= ~PS4; \
+ if(n == 3) IP3H |= PS4H, IP3 |= PS4; \
+ }while(0)
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IP = 0xB8; //жȼλ PPCA PLVD PADC PS PT1 PX1 PT0 PX0 0000,0000
+//--------
+sbit PPCA = IP^7; //PCA ģжȼ
+sbit PLVD = IP^6; //ѹжȼ
+sbit PADC = IP^5; //ADC жȼ
+sbit PS = IP^4; //ж0ȼ趨λ
+sbit PT1 = IP^3; //ʱж1ȼ趨λ
+sbit PX1 = IP^2; //ⲿж1ȼ趨λ
+sbit PT0 = IP^1; //ʱж0ȼ趨λ
+sbit PX0 = IP^0; //ⲿж0ȼ趨λ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IPH = 0xB7; //жȼλ PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H 0000,0000
+#define PPCAH 0x80
+#define PLVDH 0x40
+#define PADCH 0x20
+#define PSH 0x10
+#define PT1H 0x08
+#define PX1H 0x04
+#define PT0H 0x02
+#define PX0H 0x01
+
+//ⲿж0жȼ
+#define INT0_Priority(n) do{if(n == 0) IPH &= ~PX0H, PX0 = 0; \
+ if(n == 1) IPH &= ~PX0H, PX0 = 1; \
+ if(n == 2) IPH |= PX0H, PX0 = 0; \
+ if(n == 3) IPH |= PX0H, PX0 = 1; \
+ }while(0)
+//ⲿж1жȼ
+#define INT1_Priority(n) do{if(n == 0) IPH &= ~PX1H, PX1 = 0; \
+ if(n == 1) IPH &= ~PX1H, PX1 = 1; \
+ if(n == 2) IPH |= PX1H, PX1 = 0; \
+ if(n == 3) IPH |= PX1H, PX1 = 1; \
+ }while(0)
+//ʱ0жȼ
+#define Timer0_Priority(n) do{if(n == 0) IPH &= ~PT0H, PT0 = 0; \
+ if(n == 1) IPH &= ~PT0H, PT0 = 1; \
+ if(n == 2) IPH |= PT0H, PT0 = 0; \
+ if(n == 3) IPH |= PT0H, PT0 = 1; \
+ }while(0)
+//ʱ1жȼ
+#define Timer1_Priority(n) do{if(n == 0) IPH &= ~PT1H, PT1 = 0; \
+ if(n == 1) IPH &= ~PT1H, PT1 = 1; \
+ if(n == 2) IPH |= PT1H, PT1 = 0; \
+ if(n == 3) IPH |= PT1H, PT1 = 1; \
+ }while(0)
+//1жȼ
+#define UART1_Priority(n) do{if(n == 0) IPH &= ~PSH, PS = 0; \
+ if(n == 1) IPH &= ~PSH, PS = 1; \
+ if(n == 2) IPH |= PSH, PS = 0; \
+ if(n == 3) IPH |= PSH, PS = 1; \
+ }while(0)
+//ADCжȼ
+#define ADC_Priority(n) do{if(n == 0) IPH &= ~PADCH, PADC = 0; \
+ if(n == 1) IPH &= ~PADCH, PADC = 1; \
+ if(n == 2) IPH |= PADCH, PADC = 0; \
+ if(n == 3) IPH |= PADCH, PADC = 1; \
+ }while(0)
+//ѹжȼ
+#define LVD_Priority(n) do{if(n == 0) IPH &= ~PLVDH, PADC = 0; \
+ if(n == 1) IPH &= ~PLVDH, PADC = 1; \
+ if(n == 2) IPH |= PLVDH, PADC = 0; \
+ if(n == 3) IPH |= PLVDH, PADC = 1; \
+ }while(0)
+//CCP/PCA/PWMжȼ
+#define PCA_Priority(n) do{if(n == 0) IPH &= ~PPCAH, PPCA = 0; \
+ if(n == 1) IPH &= ~PPCAH, PPCA = 1; \
+ if(n == 2) IPH |= PPCAH, PPCA = 0; \
+ if(n == 3) IPH |= PPCAH, PPCA = 1; \
+ }while(0)
+
+//#define PCA_InterruptFirst() PPCA = 1
+//#define LVD_InterruptFirst() PLVD = 1
+//#define ADC_InterruptFirst() PADC = 1
+//#define UART1_InterruptFirst() PS = 1
+//#define Timer1_InterruptFirst() PT1 = 1
+//#define INT1_InterruptFirst() PX1 = 1
+//#define Timer0_InterruptFirst() PT0 = 1
+//#define INT0_InterruptFirst() PX0 = 1
+
+
+/*************************************************************************************************/
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr CMPCR1 = 0xE6; CMPEN CMPIF PIE NIE PIS NIS CMPOE CMPRES 00000000B
+#define CMPEN 0x80 //1: Ƚ, 0: ֹ,رձȽԴ
+#define CMPIF 0x40 //Ƚжϱ־, ػ½ж, 0
+#define PIE 0x20 //1: ȽϽ01, ж
+#define NIE 0x10 //1: ȽϽ10, ½ж
+#define PIS 0x08 //ѡ, 0: ѡڲP3.7, 1: ADC_CHS[3:0]ѡADC.
+#define NIS 0x04 //븺ѡ, 0: ѡڲBandGapѹBGv, 1: ѡⲿP3.6.
+#define CMPOE 0x02 //1: ȽϽ, 0: ֹ.
+#define CMPRES 0x01 //ȽϽ, 1: CMP+ƽCMP-, 0: CMP+ƽCMP-, ֻ
+
+#define CMP_P_P37 0x00 //ѡ, 0: ѡڲP3.7
+#define CMP_P_ADC 0x08 //ѡ, 1: ADC_CHS[3:0]ѡADC.
+#define CMP_N_GAP 0x00 //븺ѡ, 0: ѡڲBandGapѹBGv.
+#define CMP_N_P36 0x04 //븺ѡ, 1: ѡⲿP3.6.
+
+#define CMPO_P34() P_SW2 &= ~0x08 //P3.4.
+#define CMPO_P41() P_SW2 |= 0x08 //P4.1.
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr CMPCR2 = 0xE7; INVCMPO DISFLT LCDTY[5:0] 00001001B
+#define INVCMPO 0x80 //1: ȽIOȡ, 0: ȡ
+#define DISFLT 0x40 //1: ر0.1uF˲, 0:
+#define LCDTY 0x00 //0~63, ȽϽ仯ʱ
+
+
+
+/*************************************************************************************************/
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr SCON = 0x98; SM0 SM1 SM2 REN TB8 RB8 TI RI 00000000B //S1 Control
+
+#define S1_DoubleRate() PCON |= 0x80
+#define S1_SHIFT() SCON &= 0x3f
+
+#define S1_8bit() SCON = (SCON & 0x3f) | 0x40
+#define S1_9bit() SCON = (SCON & 0x3f) | 0xc0
+#define S1_RX_Enable() SCON |= 0x10
+#define S1_RX_Disable() SCON &= ~0x10
+#define TI1 TI /* жTI1Ƿ */
+#define RI1 RI /* жRI1Ƿ */
+#define SET_TI1() TI = 1 /* TI1(ж) */
+#define CLR_TI1() TI = 0 /* TI1 */
+#define CLR_RI1() RI = 0 /* RI1 */
+#define S1TB8_SET() TB8 = 1 /* TB8 */
+#define S1TB8_CLR() TB8 = 0 /* TB8 */
+#define S1_Int_Enable() ES = 1 /* 1ж */
+#define S1_Int_Disable() ES = 0 /* 1ֹж */
+#define S1_BRT_UseTimer1() AUXR &= ~1
+#define S1_BRT_UseTimer2() AUXR |= 1
+#define S1_USE_P30P31() P_SW1 &= ~0xc0 //UART1 ʹP30 P31 Ĭ
+#define S1_USE_P36P37() P_SW1 = (P_SW1 & ~0xc0) | 0x40 //UART1 ʹP36 P37
+#define S1_USE_P16P17() P_SW1 = (P_SW1 & ~0xc0) | 0x80 //UART1 ʹP16 P17
+#define S1_USE_P43P44() P_SW1 |= 0xc0 //UART1 ʹP43 P44
+//#define S1_TXD_RXD_SHORT() PCON2 |= (1<<4) //TXDRXDм
+//#define S1_TXD_RXD_OPEN() PCON2 &= ~(1<<4) //TXDRXDм̶Ͽ Ĭ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr S2CON = 0x9A; S2SM0 - S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B //S2 Control
+
+#define S2_MODE0() S2CON &= ~(1<<7) /* 2ģʽ08λUART = ʱ2 / 4 */
+#define S2_MODE1() S2CON |= (1<<7) /* 2ģʽ19λUART = ʱ2 / 4 */
+#define S2_8bit() S2CON &= ~(1<<7) /* 2ģʽ08λUART = ʱ2 / 4 */
+#define S2_9bit() S2CON |= (1<<7) /* 2ģʽ19λUART = ʱ2 / 4 */
+#define S2_RX_Enable() S2CON |= (1<<4) /* 2 */
+#define S2_RX_Disable() S2CON &= ~(1<<4) /* ֹ2 */
+#define TI2 (S2CON & 2) /* жTI2Ƿ */
+#define RI2 (S2CON & 1) /* жRI2Ƿ */
+#define SET_TI2() S2CON |= (1<<1) /* TI2(ж) */
+#define CLR_TI2() S2CON &= ~(1<<1) /* TI2 */
+#define CLR_RI2() S2CON &= ~1 /* RI2 */
+#define S2TB8_SET() S2CON |= (1<<3) /* TB8 */
+#define S2TB8_CLR() S2CON &= ~(1<<3) /* TB8 */
+#define S2_Int_Enable() IE2 |= 1 /* 2ж */
+#define S2_Int_Disable() IE2 &= ~1 /* 2ֹж */
+#define S2_USE_P10P11() P_SW2 &= ~1 /* UART2 ʹP1 Ĭ */
+#define S2_USE_P46P47() P_SW2 |= 1 /* UART2 ʹP4 */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr S3CON = 0xAC; S3SM0 S3ST3 S3SM2 S3REN S3TB8 S3RB8 S3TI S3RI 00000000B //S3 Control
+
+#define S3_MODE0() S3CON &= ~(1<<7) /* 3ģʽ08λUART = ʱ / 4 */
+#define S3_MODE1() S3CON |= (1<<7) /* 3ģʽ19λUART = ʱ / 4 */
+#define S3_8bit() S3CON &= ~(1<<7) /* 3ģʽ08λUART = ʱ / 4 */
+#define S3_9bit() S3CON |= (1<<7) /* 3ģʽ19λUART = ʱ / 4 */
+#define S3_RX_Enable() S3CON |= (1<<4) /* 3 */
+#define S3_RX_Disable() S3CON &= ~(1<<4) /* ֹ3 */
+#define TI3 (S3CON & 2) != 0 /* жTI3Ƿ */
+#define RI3 (S3CON & 1) != 0 /* жRI3Ƿ */
+#define SET_TI3() S3CON |= (1<<1) /* TI3(ж) */
+#define CLR_TI3() S3CON &= ~(1<<1) /* TI3 */
+#define CLR_RI3() S3CON &= ~1 /* RI3 */
+#define S3TB8_SET() S3CON |= (1<<3) /* TB8 */
+#define S3TB8_CLR() S3CON &= ~(1<<3) /* TB8 */
+#define S3_Int_Enable() IE2 |= (1<<3) /* 3ж */
+#define S3_Int_Disable() IE2 &= ~(1<<3) /* 3ֹж */
+#define S3_BRT_UseTimer3() S3CON |= (1<<6) /* BRT select Timer3 */
+#define S3_BRT_UseTimer2() S3CON &= ~(1<<6) /* BRT select Timer2 */
+#define S3_USE_P00P01() P_SW2 &= ~2 /* UART3 ʹP0 Ĭ */
+#define S3_USE_P50P51() P_SW2 |= 2 /* UART3 ʹP5 */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr S4CON = 0x84; S4SM0 S4ST4 S4SM2 S4REN S4TB8 S4RB8 S4TI S4RI 00000000B //S4 Control
+
+#define S4_MODE0() S4CON &= ~(1<<7) /* 4ģʽ08λUART = ʱ / 4 */
+#define S4_MODE1() S4CON |= (1<<7) /* 4ģʽ19λUART = ʱ / 4 */
+#define S4_8bit() S4CON &= ~(1<<7) /* 4ģʽ08λUART = ʱ / 4 */
+#define S4_9bit() S4CON |= (1<<7) /* 4ģʽ19λUART = ʱ / 4 */
+#define S4_RX_Enable() S4CON |= (1<<4) /* 4 */
+#define S4_RX_Disable() S4CON &= ~(1<<4) /* ֹ4 */
+#define TI4 (S4CON & 2) != 0 /* жTI3Ƿ */
+#define RI4 (S4CON & 1) != 0 /* жRI3Ƿ */
+#define SET_TI4() S4CON |= 2 /* TI3(ж) */
+#define CLR_TI4() S4CON &= ~2 /* TI3 */
+#define CLR_RI4() S4CON &= ~1 /* RI3 */
+#define S4TB8_SET() S4CON |= 8 /* TB8 */
+#define S4TB8_CLR() S4CON &= ~8 /* TB8 */
+#define S4_Int_Enable() IE2 |= (1<<4) /* 4ж */
+#define S4_Int_Disable() IE2 &= ~(1<<4) /* 4ֹж */
+#define S4_BRT_UseTimer4() S4CON |= (1<<6) /* BRT select Timer4 */
+#define S4_BRT_UseTimer2() S4CON &= ~(1<<6) /* BRT select Timer2 */
+#define S4_USE_P02P03() P_SW2 &= ~4 /* UART4 ʹP0 Ĭ */
+#define S4_USE_P52P53() P_SW2 |= 4 /* UART4 ʹP5 */
+
+
+
+/**********************************************************/
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr AUXR = 0x8E; T0x12 T1x12 UART_M0x6 T2R T2_C/T T2x12 EXTRAM S1ST2 0000,0000 //Auxiliary Register
+
+#define InternalXdata_Disable() AUXR |= 2 /* ֹʹڲxdata, зxdataǷⲿxdata */
+#define InternalXdata_Enable() AUXR &= ~2 /* ʹڲxdata, ʵĵַڲxdataΧʱ, ڲxadta, ַڲxdataʱ, ⲿxdata */
+#define S1_M0x6() AUXR |= (1<<5) /* UART Mode0 Speed is 6x Standard */
+#define S1_M0x1() AUXR &= ~(1<<5) /* default, UART Mode0 Speed is Standard */
+
+//====================================
+#define Timer0_16bitAutoReload() TMOD &= ~0x03 /* 16λԶװ */
+#define Timer0_16bit() TMOD = (TMOD & ~0x03) | 0x01 /* 16λ */
+#define Timer0_8bitAutoReload() TMOD = (TMOD & ~0x03) | 0x02 /* 8λԶװ */
+#define Timer0_16bitAutoRL_NoMask() TMOD |= 0x03 /* 16λԶװж */
+#define Timer0_Run() TR0 = 1 /* ʱ0 */
+#define Timer0_Stop() TR0 = 0 /* ֹʱ0 */
+#define Timer0_Gate_INT0_P32() TMOD |= (1<<3) /* ʱ0ⲿINT0ߵƽʱ */
+#define Timer0_AsTimer() TMOD &= ~(1<<2) /* ʱ0ʱ */
+#define Timer0_AsCounter() TMOD |= (1<<2) /* ʱ0 */
+#define Timer0_AsCounterP34() TMOD |= (1<<2) /* ʱ0 */
+#define Timer0_1T() AUXR |= (1<<7) /* Timer0 clodk = fo */
+#define Timer0_12T() AUXR &= ~(1<<7) /* Timer0 clodk = fo/12 12Ƶ, default */
+#define Timer0_CLKO_Enable() INT_CLKO |= 1 /* T0 T0(P3.5)Fck0 = 1/2 T0 ʣT01T12T */
+#define Timer0_CLKO_Disable() INT_CLKO &= ~1
+#define Timer0_CLKO_Enable_P34() INT_CLKO |= 1 /* T0 T0(P3.5)Fck0 = 1/2 T0 ʣT01T12T */
+#define Timer0_CLKO_Disable_P34() INT_CLKO &= ~1
+#define Timer0_InterruptEnable() ET0 = 1 /* Timer1ж.*/
+#define Timer0_InterruptDisable() ET0 = 0 /* ֹTimer1ж.*/
+
+#define T0_Load(n) TH0 = (n) / 256, TL0 = (n) % 256
+#define T0_Load_us_1T(n) Timer0_AsTimer(),Timer0_1T(), Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/1000)*(n))/1000)/256, TL0=(65536-((MAIN_Fosc/1000)*(n))/1000)%256
+#define T0_Load_us_12T(n) Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/12000)*(n))/1000)/256,TL0=(65536-((MAIN_Fosc/12000)*(n))/1000)%256
+#define T0_Frequency_1T_P35(n) ET0=0,Timer0_AsTimer(),Timer0_1T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit0,TR0=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */
+#define T0_Frequency_12T_P35(n) ET0=0,Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit0,TR0=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */
+
+//====================================
+#define Timer1_16bitAutoReload() TMOD &= ~0x30 /* 16λԶװ */
+#define Timer1_16bit() TMOD = (TMOD & ~0x30) | 0x10 /* 16λ */
+#define Timer1_8bitAutoReload() TMOD = (TMOD & ~0x30) | 0x20 /* 8λԶװ */
+#define Timer1_Run() TR1 = 1 /* ʱ1 */
+#define Timer1_Stop() TR1 = 0 /* ֹʱ1 */
+#define Timer1_Gate_INT1_P33() TMOD |= (1<<7) /* ʱ1ⲿINT1ߵƽʱ */
+#define Timer1_AsTimer() TMOD &= ~(1<<6) /* ʱ1ʱ */
+#define Timer1_AsCounter() TMOD |= (1<<6) /* ʱ1 */
+#define Timer1_AsCounterP35() TMOD |= (1<<6) /* ʱ1 */
+#define Timer1_1T() AUXR |= (1<<6) /* Timer1 clodk = fo */
+#define Timer1_12T() AUXR &= ~(1<<6) /* Timer1 clodk = fo/12 12Ƶ, default */
+#define Timer1_CLKO_Enable() INT_CLKO |= 2 /* T1 T1(P3.4)Fck1 = 1/2 T1 ʣT11T12T */
+#define Timer1_CLKO_Disable() INT_CLKO &= ~2
+#define Timer1_CLKO_Enable_P35() INT_CLKO |= 2 /* T1 T1(P3.4)Fck1 = 1/2 T1 ʣT11T12T */
+#define Timer1_CLKO_Disable_P35() INT_CLKO &= ~2
+#define Timer1_InterruptEnable() ET1 = 1 /* Timer1ж. */
+#define Timer1_InterruptDisable() ET1 = 0 /* ֹTimer1ж. */
+
+#define T1_Load(n) TH1 = (n) / 256, TL1 = (n) % 256
+#define T1_Load_us_1T(n) Timer1_AsTimer(),Timer1_1T(), Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
+#define T1_Load_us_12T(n) Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
+#define T1_Frequency_1T_P34(n) ET1=0,Timer1_AsTimer(),Timer1_1T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit1,TR1=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */
+#define T1_Frequency_12T_P34(n) ET1=0,Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit1,TR1=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */
+
+//====================================
+#define Timer2_Run() AUXR |= (1<<4) /* ʱ2 */
+#define Timer2_Stop() AUXR &= ~(1<<4) /* ֹʱ2 */
+#define Timer2_AsTimer() AUXR &= ~(1<<3) /* ʱ2ʱ */
+#define Timer2_AsCounter() AUXR |= (1<<3) /* ʱ2 */
+#define Timer2_AsCounterP31() AUXR |= (1<<3) /* ʱ2 */
+#define Timer2_1T() AUXR |= (1<<2) /* Timer0 clock = fo */
+#define Timer2_12T() AUXR &= ~(1<<2) /* Timer0 clock = fo/12 12Ƶ, default */
+#define Timer2_CLKO_Enable() INT_CLKO |= 4 /* T2 P1.3Fck2 = 1/2 T2 ʣT21T12T */
+#define Timer2_CLKO_Disable() INT_CLKO &= ~4
+#define Timer2_CLKO_Enable_P13() INT_CLKO |= 4 /* T2 P1.3Fck2 = 1/2 T2 ʣT21T12T */
+#define Timer2_CLKO_Disable_P13() INT_CLKO &= ~4
+#define Timer2_InterruptEnable() IE2 |= (1<<2) /* Timer2ж. */
+#define Timer2_InterruptDisable() IE2 &= ~(1<<2) /* ֹTimer2ж. */
+
+#define T2_Load(n) TH2 = (n) / 256, TL2 = (n) % 256
+#define T2_Load_us_1T(n) Timer2_AsTimer(),Timer2_1T(), TH2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
+#define T2_Load_us_12T(n) Timer2_AsTimer(),Timer2_12T(),TH2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
+#define T2_Frequency_1T_P30(n) Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_1T(), TH2=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL2=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer2_CLKO_Enable_P30(),Timer2_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */
+#define T2_Frequency_12T_P30(n) Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_12T(),TH2=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL2=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer2_CLKO_Enable_P30(),Timer2_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */
+
+//====================================
+#define Timer3_Run() T4T3M |= (1<<3) /* ʱ3 */
+#define Timer3_Stop() T4T3M &= ~(1<<3) /* ֹʱ3 */
+#define Timer3_AsTimer() T4T3M &= ~(1<<2) /* ʱ3ʱ */
+#define Timer3_AsCounter() T4T3M |= (1<<2) /* ʱ3, P0.5Ϊⲿ */
+#define Timer3_AsCounterP05() T4T3M |= (1<<2) /* ʱ3, P0.5Ϊⲿ */
+#define Timer3_1T() T4T3M |= (1<<1) /* 1Tģʽ */
+#define Timer3_12T() T4T3M &= ~(1<<1) /* 12Tģʽ, default */
+#define Timer3_CLKO_Enable() T4T3M |= 1 /* T3T3(P0.4)Fck = 1/2 T2 ʣT21T12T */
+#define Timer3_CLKO_Disable() T4T3M &= ~1 /* ֹT3T3(P0.4) */
+#define Timer3_CLKO_Enable_P04() T4T3M |= 1 /* T3T3(P0.4)Fck = 1/2 T2 ʣT21T12T */
+#define Timer3_CLKO_Disable_P04() T4T3M &= ~1 /* ֹT3T3(P0.4) */
+#define Timer3_InterruptEnable() IE2 |= (1<<5) /* Timer3ж. */
+#define Timer3_InterruptDisable() IE2 &= ~(1<<5) /* ֹTimer3ж. */
+
+#define T3_Load(n) TH3 = (n) / 256, TL3 = (n) % 256
+#define T3_Load_us_1T(n) Timer3_AsTimer(),Timer3_1T(), TH3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
+#define T3_Load_us_12T(n) Timer3_AsTimer(),Timer3_12T(),TH3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
+#define T3_Frequency_1T_P04(n) Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_1T(), TH3=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL3=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer3_CLKO_P04_Enable,Timer3_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */
+#define T3_Frequency_12T_P04(n) Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_12T(),TH3=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL3=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer3_CLKO_P04_Enable,Timer3_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */
+
+//====================================
+#define Timer4_Run() T4T3M |= (1<<7) /* ʱ4 */
+#define Timer4_Stop() T4T3M &= ~(1<<7) /* ֹʱ4 */
+#define Timer4_AsTimer() T4T3M &= ~(1<<6) /* ʱ4ʱ */
+#define Timer4_AsCounter() T4T3M |= (1<<6) /* ʱ4, P0.7Ϊⲿ */
+#define Timer4_AsCounterP07() T4T3M |= (1<<6) /* ʱ4, P0.7Ϊⲿ */
+#define Timer4_1T() T4T3M |= (1<<5) /* 1Tģʽ */
+#define Timer4_12T() T4T3M &= ~(1<<5) /* 12Tģʽ, default */
+#define Timer4_CLKO_Enable() T4T3M |= (1<<4) /* T4T4(P0.6)Fck = 1/2 T2 ʣT21T12T */
+#define Timer4_CLKO_Disable() T4T3M &= ~(1<<4) /* ֹT4T4(P0.6) */
+#define Timer4_CLKO_Enable_P06() T4T3M |= (1<<4) /* T4T4(P0.6)Fck = 1/2 T2 ʣT21T12T */
+#define Timer4_CLKO_Disable_P06() T4T3M &= ~(1<<4) /* ֹT4T4(P0.6) */
+#define Timer4_InterruptEnable() IE2 |= (1<<6) /* Timer4ж. */
+#define Timer4_InterruptDisable() IE2 &= ~(1<<6) /* ֹTimer4ж. */
+
+#define T4_Load(n) TH4 = (n) / 256, TL4 = (n) % 256
+#define T4_Load_us_1T(n) Timer4_AsTimer(),Timer4_1T(), TH4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
+#define T4_Load_us_12T(n) Timer4_AsTimer(),Timer4_12T(),TH4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
+#define T4_Frequency_1T_P06(n) Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_1T(), TH4=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL4=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer4_CLKO_P06_Enable(),Timer4_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */
+#define T4_Frequency_12T_P06(n) Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_12T(),TH4=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL4=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer4_CLKO_P06_Enable(),Timer4_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */
+//====================================================================================================================
+
+//sfr WDT_CONTR = 0xC1; //Watch-Dog-Timer Control register
+// 7 6 5 4 3 2 1 0 Reset Value
+// WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0 xx00,0000
+#define D_WDT_FLAG (1<<7)
+#define D_EN_WDT (1<<5)
+#define D_CLR_WDT (1<<4) /* auto clear */
+#define D_IDLE_WDT (1<<3) /* WDT counter when Idle */
+#define D_WDT_SCALE_2 0
+#define D_WDT_SCALE_4 1
+#define D_WDT_SCALE_8 2 /* T=393216*N/fo */
+#define D_WDT_SCALE_16 3
+#define D_WDT_SCALE_32 4
+#define D_WDT_SCALE_64 5
+#define D_WDT_SCALE_128 6
+#define D_WDT_SCALE_256 7
+
+#define WDT_PS_Set(n) WDT_CONTR = (WDT_CONTR & ~0x07) | (n & 0x07) /* ŹʱʱӷƵϵ */
+#define WDT_reset(n) WDT_CONTR = D_EN_WDT + D_CLR_WDT + D_IDLE_WDT + (n) /* ʼWDTι */
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PCON = 0x87; SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0001,0000 //Power Control
+//SMOD //˫
+//SMOD0
+#define LVDF (1<<5) /* P4.6ѹ־ */
+//POF
+//GF1
+//GF0
+//#define D_PD 2 /* set 1, power down mode */
+//#define D_IDLE 1 /* set 1, idle mode */
+#define MCU_IDLE() PCON |= 1 /* MCU IDLE ģʽ */
+#define MCU_POWER_DOWN() PCON |= 2 /* MCU ˯ ģʽ */
+
+
+//sfr IAP_CMD = 0xC5;
+#define IAP_STANDBY() IAP_CMD = 0 //IAPֹ
+#define IAP_READ() IAP_CMD = 1 //IAP
+#define IAP_WRITE() IAP_CMD = 2 //IAPд
+#define IAP_ERASE() IAP_CMD = 3 //IAP
+
+//sfr IAP_TRIG = 0xC6;
+#define IAP_TRIG() IAP_TRIG = 0x5A, IAP_TRIG = 0xA5 /* IAP */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr IAP_CONTR = 0xC7; IAPEN SWBS SWRST CFAIL - - - - 0000,x000 //IAP Control Register
+
+#define IAP_EN (1<<7)
+#define IAP_SWBS (1<<6)
+#define IAP_SWRST (1<<5)
+#define IAP_CMD_FAIL (1<<4)
+
+#define IAP_ENABLE() IAP_CONTR = IAP_EN; IAP_TPS = MAIN_Fosc / 1000000
+#define IAP_DISABLE() IAP_CONTR = 0; IAP_CMD = 0; IAP_TRIG = 0; IAP_ADDRH = 0xff; IAP_ADDRL = 0xff
+
+
+/* ADC Register */
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr ADC_CONTR = 0xBC; ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000,0000 /* AD תƼĴ */
+//sfr ADC_RES = 0xBD; ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 0000,0000 /* A/D ת8λ */
+//sfr ADC_RESL = 0xBE; ADCV.1 ADCV.0 0000,0000 /* A/D ת2λ */
+//sfr ADC_CONTR = 0xBC; //ֱMOVҪ
+
+
+//sfr SPCTL = 0xCE; SPIƼĴ
+// 7 6 5 4 3 2 1 0 Reset Value
+// SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0x00
+
+#define SPI_SSIG_None() SPCTL |= (1<<7) /* 1: SS */
+#define SPI_SSIG_Enable() SPCTL &= ~(1<<7) /* 0: SSھӻ */
+#define SPI_Enable() SPCTL |= (1<<6) /* 1: SPI */
+#define SPI_Disable() SPCTL &= ~(1<<6) /* 0: ֹSPI */
+#define SPI_LSB_First() SPCTL |= (1<<5) /* 1: LSBȷ */
+#define SPI_MSB_First() SPCTL &= ~(1<<5) /* 0: MSBȷ */
+#define SPI_Master() SPCTL |= (1<<4) /* 1: Ϊ */
+#define SPI_Slave() SPCTL &= ~(1<<4) /* 0: Ϊӻ */
+#define SPI_SCLK_NormalH() SPCTL |= (1<<3) /* 1: ʱSCLKΪߵƽ */
+#define SPI_SCLK_NormalL() SPCTL &= ~(1<<3) /* 0: ʱSCLKΪ͵ƽ */
+#define SPI_PhaseH() SPCTL |= (1<<2) /* 1: */
+#define SPI_PhaseL() SPCTL &= ~(1<<2) /* 0: */
+#define SPI_Speed(n) SPCTL = (SPCTL & ~3) | (n) /*ٶ, 0 -- fosc/4, 1 -- fosc/8, 2 -- fosc/16, 3 -- fosc/32 */
+
+//sfr SPDAT = 0xCF; //SPI Data Register 0000,0000
+//sfr SPSTAT = 0xCD; //SPI״̬Ĵ
+// 7 6 5 4 3 2 1 0 Reset Value
+// SPIF WCOL - - - - - -
+#define SPIF 0x80 /* SPIɱ־д10*/
+#define WCOL 0x40 /* SPIдͻ־д10 */
+
+#define SPI_USE_P12P13P14P15() P_SW1 &= ~0x0c /* SPIлP12(SS) P13(MOSI) P14(MISO) P15(SCLK)(ϵĬ)*/
+#define SPI_USE_P22P23P24P25() P_SW1 = (P_SW1 & ~0x0c) | 0x04 /* SPIлP22(SS) P23(MOSI) P24(MISO) P25(SCLK)*/
+#define SPI_USE_P74P75P76P77() P_SW1 = (P_SW1 & ~0x0c) | 0x08 /* SPIлP74(SS) P75(MOSI) P76(MISO) P77(SCLK)*/
+#define SPI_USE_P35P34P33P32() P_SW1 = P_SW1 | 0x0C /* SPIлP35(SS) P34(MOSI) P33(MISO) P32(SCLK)*/
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CCFG = 0xFE80H; ENI2C MSSL MSSPEED[5:0] 0000,0000 /* I2CüĴ */
+#define I2C_Function(n) (n==0?(I2CCFG &= ~0x80):(I2CCFG |= 0x80)) //0ֹ I2C ܣ1ʹ I2C
+#define I2C_ENABLE() I2CCFG |= 0x80 /* ʹ I2C */
+#define I2C_DISABLE() I2CCFG &= ~0x80 /* ֹ I2C */
+#define I2C_Master() I2CCFG |= 0x40 /* 1: Ϊ */
+#define I2C_Slave() I2CCFG &= ~0x40 /* 0: Ϊӻ */
+#define I2C_SetSpeed(n) I2CCFG = (I2CCFG & ~0x3f) | (n & 0x3f) /* ٶ=Fosc/2/(Speed*2+4) */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CMSCR = 0xFE81H; EMSI - - - MSCMD[3:0] 0000,0000 /* I2CüĴ */
+#define I2C_Master_Inturrupt(n) (n==0?(I2CMSCR &= ~0x80):(I2CMSCR |= 0x80)) //0ֹ I2C ܣ1ʹ I2C
+
+#define I2C_CMD_None 0
+#define I2C_CMD_Start 1
+#define I2C_CMD_Send 2
+#define I2C_CMD_RACK 3
+#define I2C_CMD_Read 4
+#define I2C_CMD_SACK 5
+#define I2C_CMD_Stop 6
+#define I2C_CMD_RFU1 7
+#define I2C_CMD_RFU2 8
+#define I2C_CMD_Start_Send_RACK 9
+#define I2C_CMD_Send_RACK 10
+#define I2C_CMD_Read_SACK 11
+#define I2C_CMD_Read_SNAK 12
+
+#define I2C_Command(n) I2CMSCR = (I2CMSCR & ~0x0f) | (n & 0x0f) /* */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CMSST = 0xFE82H; MSBUSY MSIF - - - - MSACKI MSACKO 0000,0000 /* I2C״̬Ĵ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CMSAUX = 0xFE88H; - - - - - - - WDTA 0000,0000 /* I2CƼĴ */
+#define I2C_WDTA_EN() I2CMSAUX |= 0x01 /* ʹԶ */
+#define I2C_WDTA_DIS() I2CMSAUX &= ~0x01 /* ֹԶ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CSLCR = 0xFE83H; - ESTAI ERXI ETXI ESTOI - - SLRET 0000,0000 /* I2CӻƼĴ */
+#define I2C_ESTAI_EN() I2CSLCR |= 0x40 /* ʹܴӻSTARTźж */
+#define I2C_ESTAI_DIS() I2CSLCR &= ~0x40 /* ֹӻSTARTźж */
+#define I2C_ERXI_EN() I2CSLCR |= 0x20 /* ʹܴӻ1ֽж */
+#define I2C_ERXI_DIS() I2CSLCR &= ~0x20 /* ֹӻ1ֽж */
+#define I2C_ETXI_EN() I2CSLCR |= 0x10 /* ʹܴӻ1ֽж */
+#define I2C_ETXI_DIS() I2CSLCR &= ~0x10 /* ֹӻ1ֽж */
+#define I2C_ESTOI_EN() I2CSLCR |= 0x08 /* ʹܴӻSTOPźж */
+#define I2C_ESTOI_DIS() I2CSLCR &= ~0x08 /* ֹӻSTOPźж */
+#define I2C_SLRET() I2CSLCR |= 0x01 /* λӻģʽ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CSLST = 0xFE84H; SLBUSY STAIF RXIF TXIF STOIF - SLACKI SLACKO 0000,0000 /* I2Cӻ״̬Ĵ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr I2CSLADR = 0xFE85H; I2CSLADR[7:1] MA 0000,0000 /* I2CӻַĴ */
+#define I2C_Address(n) I2CSLADR = (I2CSLADR & 0x01) | (n << 1) /* ӻַ */
+#define I2C_MATCH_EN() I2CSLADR &= ~0x01 /* ʹܴӻַȽϹܣֻƥַ */
+#define I2C_MATCH_DIS() I2CSLADR |= 0x01 /* ֹӻַȽϹܣ豸ַ */
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_ENO = 0xFEB1H; ENO4N ENO4P ENO3N ENO3P ENO2N ENO2P ENO1N ENO1P 0000,0000 /* ʹܼĴ */
+//sfr PWMB_ENO = 0xFEB5H; - ENO8P - ENO7P - ENO6P - ENO5P 0000,0000 /* ʹܼĴ */
+#define PWM1P_OUT_EN() PWMA_ENO |= 0x01 /* ʹ PWM1P */
+#define PWM1P_OUT_DIS() PWMA_ENO &= ~0x01 /* ֹ PWM1P */
+#define PWM1N_OUT_EN() PWMA_ENO |= 0x02 /* ʹ PWM1N */
+#define PWM1N_OUT_DIS() PWMA_ENO &= ~0x02 /* ֹ PWM1N */
+#define PWM2P_OUT_EN() PWMA_ENO |= 0x04 /* ʹ PWM2P */
+#define PWM2P_OUT_DIS() PWMA_ENO &= ~0x04 /* ֹ PWM2P */
+#define PWM2N_OUT_EN() PWMA_ENO |= 0x08 /* ʹ PWM2N */
+#define PWM2N_OUT_DIS() PWMA_ENO &= ~0x08 /* ֹ PWM2N */
+#define PWM3P_OUT_EN() PWMA_ENO |= 0x10 /* ʹ PWM3P */
+#define PWM3P_OUT_DIS() PWMA_ENO &= ~0x10 /* ֹ PWM3P */
+#define PWM3N_OUT_EN() PWMA_ENO |= 0x20 /* ʹ PWM3N */
+#define PWM3N_OUT_DIS() PWMA_ENO &= ~0x20 /* ֹ PWM3N */
+#define PWM4P_OUT_EN() PWMA_ENO |= 0x40 /* ʹ PWM3P */
+#define PWM4P_OUT_DIS() PWMA_ENO &= ~0x40 /* ֹ PWM3P */
+#define PWM4N_OUT_EN() PWMA_ENO |= 0x80 /* ʹ PWM3N */
+#define PWM4N_OUT_DIS() PWMA_ENO &= ~0x80 /* ֹ PWM3N */
+
+#define PWM5P_OUT_EN() PWMB_ENO |= 0x01 /* ʹ PWM5P */
+#define PWM5P_OUT_DIS() PWMB_ENO &= ~0x01 /* ֹ PWM5P */
+#define PWM6P_OUT_EN() PWMB_ENO |= 0x04 /* ʹ PWM6P */
+#define PWM6P_OUT_DIS() PWMB_ENO &= ~0x04 /* ֹ PWM6P */
+#define PWM7P_OUT_EN() PWMB_ENO |= 0x10 /* ʹ PWM7P */
+#define PWM7P_OUT_DIS() PWMB_ENO &= ~0x10 /* ֹ PWM7P */
+#define PWM8P_OUT_EN() PWMB_ENO |= 0x40 /* ʹ PWM8P */
+#define PWM8P_OUT_DIS() PWMB_ENO &= ~0x40 /* ֹ PWM8P */
+
+#define PWMA_OutChannelSel(n) PWMA_ENO = n //ѡͨ
+#define PWMB_OutChannelSel(n) PWMB_ENO = n //ѡͨ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_PS = 0xFEB2H; C4PS1 C4PS0 C3PS1 C3PS0 C2PS1 C2PS0 C1PS1 C1PS0 0000,0000 /* ʹܼĴ */
+//sfr PWMB_PS = 0xFEB6H; C8PS1 C8PS0 C7PS1 C7PS0 C6PS1 C6PS0 C5PS1 C5PS0 0000,0000 /* ʹܼĴ */
+
+#define PWM1_USE_P10P11() PWMA_PS = (PWMA_PS & ~0x03) /* PWM ͨ 1 лP10(PWM1P) P11(PWM1N) */
+#define PWM1_USE_P20P21() PWMA_PS = (PWMA_PS & ~0x03) | 0x01 /* PWM ͨ 1 лP20(PWM1P) P21(PWM1N) */
+#define PWM1_USE_P60P61() PWMA_PS = (PWMA_PS & ~0x03) | 0x02 /* PWM ͨ 1 лP60(PWM1P) P61(PWM1N) */
+
+#define PWM2_USE_P12P13() PWMA_PS = (PWMA_PS & ~0x0C) /* PWM ͨ 2 лP12/P54(PWM2P) P13(PWM2N) */
+#define PWM2_USE_P22P23() PWMA_PS = (PWMA_PS & ~0x0C) | 0x04 /* PWM ͨ 2 лP22(PWM2P) P23(PWM2N) */
+#define PWM2_USE_P62P63() PWMA_PS = (PWMA_PS & ~0x0C) | 0x08 /* PWM ͨ 2 лP62(PWM2P) P63(PWM2N) */
+
+#define PWM3_USE_P14P15() PWMA_PS = (PWMA_PS & ~0x30) /* PWM ͨ 3 лP14(PWM3P) P15(PWM3N) */
+#define PWM3_USE_P24P25() PWMA_PS = (PWMA_PS & ~0x30) | 0x10 /* PWM ͨ 3 лP24(PWM3P) P25(PWM3N) */
+#define PWM3_USE_P64P65() PWMA_PS = (PWMA_PS & ~0x30) | 0x20 /* PWM ͨ 3 лP64(PWM3P) P65(PWM3N) */
+
+#define PWM4_USE_P16P17() PWMA_PS = (PWMA_PS & ~0xC0) /* PWM ͨ 4 лP16(PWM4P) P17(PWM4N) */
+#define PWM4_USE_P26P27() PWMA_PS = (PWMA_PS & ~0xC0) | 0x40 /* PWM ͨ 4 лP26(PWM4P) P27(PWM4N) */
+#define PWM4_USE_P66P67() PWMA_PS = (PWMA_PS & ~0xC0) | 0x80 /* PWM ͨ 4 лP66(PWM4P) P67(PWM4N) */
+#define PWM4_USE_P34P33() PWMA_PS = (PWMA_PS | 0xC0) /* PWM ͨ 4 лP34(PWM4P) P33(PWM4N) */
+
+#define PWM5_USE_P20() PWMB_PS = (PWMB_PS & ~0x03) /* PWM ͨ 5 лP20(PWM5) */
+#define PWM5_USE_P17() PWMB_PS = (PWMB_PS & ~0x03) | 0x01 /* PWM ͨ 5 лP17(PWM5) */
+#define PWM5_USE_P00() PWMB_PS = (PWMB_PS & ~0x03) | 0x02 /* PWM ͨ 5 лP00(PWM5) */
+#define PWM5_USE_P74() PWMB_PS = (PWMB_PS | 0x03) /* PWM ͨ 5 лP74(PWM5) */
+
+#define PWM6_USE_P21() PWMB_PS = (PWMB_PS & ~0x0C) /* PWM ͨ 6 лP21(PWM6) */
+#define PWM6_USE_P54() PWMB_PS = (PWMB_PS & ~0x0C) | 0x04 /* PWM ͨ 6 лP54(PWM6) */
+#define PWM6_USE_P01() PWMB_PS = (PWMB_PS & ~0x0C) | 0x08 /* PWM ͨ 6 лP01(PWM6) */
+#define PWM6_USE_P75() PWMB_PS = (PWMB_PS | 0x0C) /* PWM ͨ 6 лP75(PWM6) */
+
+#define PWM7_USE_P22() PWMB_PS = (PWMB_PS & ~0x30) /* PWM ͨ 7 лP22(PWM7) */
+#define PWM7_USE_P33() PWMB_PS = (PWMB_PS & ~0x30) | 0x10 /* PWM ͨ 7 лP33(PWM7) */
+#define PWM7_USE_P02() PWMB_PS = (PWMB_PS & ~0x30) | 0x20 /* PWM ͨ 7 лP02(PWM7) */
+#define PWM7_USE_P76() PWMB_PS = (PWMB_PS | 0x30) /* PWM ͨ 7 лP76(PWM7) */
+
+#define PWM8_USE_P23() PWMB_PS = (PWMB_PS & ~0xC0) /* PWM ͨ 8 лP23(PWM8) */
+#define PWM8_USE_P34() PWMB_PS = (PWMB_PS & ~0xC0) | 0x40 /* PWM ͨ 8 лP34(PWM8) */
+#define PWM8_USE_P03() PWMB_PS = (PWMB_PS & ~0xC0) | 0x80 /* PWM ͨ 8 лP03(PWM8) */
+#define PWM8_USE_P77() PWMB_PS = (PWMB_PS | 0xC0) /* PWM ͨ 8 лP77(PWM8) */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_IOAUX = 0xFEB3H; AUX4N AUX4P AUX3N AUX3P AUX2N AUX2P AUX1N AUX1P 0000,0000 /* ʹܼĴ */
+//sfr PWMB_IOAUX = 0xFEB7H; - AUX8P - AUX7P - AUX6P - AUX5P 0000,0000 /* ʹܼĴ */
+#define AUX4N (1<<7)
+#define AUX4P (1<<6)
+#define AUX3N (1<<5)
+#define AUX3P (1<<4)
+#define AUX2N (1<<3)
+#define AUX2P (1<<2)
+#define AUX1N (1<<1)
+#define AUX1P (1)
+
+#define AUX8P (1<<6)
+#define AUX7P (1<<4)
+#define AUX6P (1<<2)
+#define AUX5P (1)
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CR1 = 0xFEC0H; ARPEA CMSA1 CMSA0 DIRA OPMA URSA UDISA CENA 0000,0000 /* ƼĴ 1 */
+//sfr PWMB_CR1 = 0xFEE0H; ARPEB CMSB1 CMSB0 DIRB OPMB URSB UDISB CENB 0000,0000 /* ƼĴ 1 */
+#define ARPE1 (1<<7)
+#define ARPE2 (1<<7)
+#define PWMA_AlignMode_Edge() PWMA_CR1 = (PWMA_CR1 & ~0x60)
+#define PWMA_AlignMode_Mid1() PWMA_CR1 = (PWMA_CR1 & ~0x60) | 0x20
+#define PWMA_AlignMode_Mid2() PWMA_CR1 = (PWMA_CR1 & ~0x60) | 0x40
+#define PWMA_AlignMode_Mid3() PWMA_CR1 = (PWMA_CR1 | 0x60)
+#define PWMA_DIR_UP() PWMA_CR1 &= ~0x10
+#define PWMA_DIR_DN() PWMA_CR1 |= 0x10
+#define PWMA_OPMA(n) (n==0?(PWMA_CR1 &= ~0x08):(PWMA_CR1 |= 0x08)) //ģʽ 0ڷ¼ʱֹͣ1ڷһθ¼ʱ CEN λֹͣ
+#define PWMA_URSA(n) (n==0?(PWMA_CR1 &= ~0x04):(PWMA_CR1 |= 0x04)) //Դ
+#define PWMA_UDISA(n) (n==0?(PWMA_CR1 &= ~0x02):(PWMA_CR1 |= 0x02)) //ֹ 0£UEV¼1¼
+#define PWMA_CEN_Enable() PWMA_CR1 |= 0x01 //1ʹܼ
+#define PWMA_CEN_Disable() PWMA_CR1 &= ~0x01 //0ֹ
+
+#define PWMB_AlignMode_Edge() PWMB_CR1 = (PWMB_CR1 & ~0x60)
+#define PWMB_AlignMode_Mid1() PWMB_CR1 = (PWMB_CR1 & ~0x60) | 0x20
+#define PWMB_AlignMode_Mid2() PWMB_CR1 = (PWMB_CR1 & ~0x60) | 0x40
+#define PWMB_AlignMode_Mid3() PWMB_CR1 = (PWMB_CR1 | 0x60)
+#define PWMB_DIR_UP() PWMB_CR1 &= ~0x10
+#define PWMB_DIR_DN() PWMB_CR1 |= 0x10
+#define PWMB_OPMB(n) (n==0?(PWMB_CR1 &= ~0x08):(PWMB_CR1 |= 0x08)) //ģʽ 0ڷ¼ʱֹͣ1ڷһθ¼ʱ CEN λֹͣ
+#define PWMB_URSB(n) (n==0?(PWMB_CR1 &= ~0x04):(PWMB_CR1 |= 0x04)) //Դ
+#define PWMB_UDISB(n) (n==0?(PWMB_CR1 &= ~0x02):(PWMB_CR1 |= 0x02)) //ֹ 0£UEV¼1¼
+#define PWMB_CEN_Enable() PWMB_CR1 |= 0x01 //1ʹܼ
+#define PWMB_CEN_Disable() PWMB_CR1 &= ~0x01 //0ֹ
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CR2 = 0xFEC1H; TI1S MMSA2 MMSA1 MMSA0 - COMSA - CCPCA 0000,x0x0 /* ƼĴ 2 */
+//sfr PWMB_CR2 = 0xFEE1H; TI5S MMSB2 MMSB1 MMSB0 - COMSB - CCPCB 0000,x0xx /* ƼĴ 2 */
+#define PWM1P_TI1() PWMA_CR2 &= ~0x80
+#define PWM1P2P3P_XOR_TI1() PWMA_CR2 |= 0x80
+#define PWM5P_TI2() PWMB_CR2 &= ~0x80
+#define PWM5P6P7P_XOR_TI2() PWMB_CR2 |= 0x80
+
+#define MMSn_RESET 0 //λ
+#define MMSn_ENABLE 1 //ʹ
+#define MMSn_UPDATE 2 //
+#define MMSn_COMP_TRGO 3 //Ƚ
+#define MMSn_OC1REF_TRGO 4 //Ƚ
+#define MMSn_OC2REF_TRGO 5 //Ƚ
+#define MMSn_OC3REF_TRGO 6 //Ƚ
+#define MMSn_OC4REF_TRGO 7 //Ƚ
+
+#define PWMA_MainModeSel(n) PWMA_CR2 = (PWMA_CR2 & ~0x70) | (n<<4) //ģʽѡ
+#define PWMB_MainModeSel(n) PWMB_CR2 = (PWMB_CR2 & ~0x70) | (n<<4) //ģʽѡ
+
+//0 CCPC=1 ʱֻ COMG λ 1 ʱЩλű
+//1 CCPC=1 ʱֻ COMG λ 1 TRGI صʱЩλű
+#define PWMA_COMSUpdateCtrl(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x04):(PWMA_CR2 |= 0x04)) ///ȽϿλĸ¿ѡ
+#define PWMB_COMSUpdateCtrl(n) PWMB_CR2 = (n==0?(PWMB_CR2 &= ~0x04):(PWMB_CR2 |= 0x04)) ///ȽϿλĸ¿ѡ
+//0 CCIE CCINE CCiP CCiNP OCIM λԤװص
+//1 CCIE CCINE CCiP CCiNP OCIM λԤװصģøλֻ COMGλ¡
+#define PWMA_CCPCAPreloaded(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x01):(PWMA_CR2 |= 0x01)) ///ȽԤװؿλ(λֻԾлͨ)
+#define PWMB_CCPCBPreloaded(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x01):(PWMA_CR2 |= 0x01)) ///ȽԤװؿλ(λֻԾлͨ)
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_SMCR = 0xFEC2H; MSMA TSA2 TSA1 TSA0 - SMSA2 SMSA1 SMSA0 0000,x000 /* ģʽƼĴ */
+//sfr PWMB_SMCR = 0xFEE2H; MSMB TSB2 TSB1 TSB0 - SMSB2 SMSB1 SMSB0 0000,x000 /* ģʽƼĴ */
+#define SMCR_TSn_ITR2 2
+#define SMCR_TSn_EDGE 4
+#define SMCR_TSn_TIMER1 5
+#define SMCR_TSn_TIMER2 6
+#define SMCR_TSn_ETRF 7
+
+#define PWMA_SMCR_Source(n) PWMA_SMCR = (PWMA_SMCR & ~0x70) | (n<<4) //Դѡ
+#define PWMB_SMCR_Source(n) PWMB_SMCR = (PWMB_SMCR & ~0x70) | (n<<4) //Դѡ
+
+#define SMCR_SMSA_INSIDE_CLK 0
+#define SMCR_SMSA_ENCODER_M1 1
+#define SMCR_SMSA_ENCODER_M2 2
+#define SMCR_SMSA_ENCODER_M3 3
+#define SMCR_SMSA_RESET 4
+#define SMCR_SMSA_GATE 5
+#define SMCR_SMSA_TRIG 6
+#define SMCR_SMSA_EXT_CLK 7
+
+#define PWMA_SMCR_SMS(n) PWMA_SMCR = (PWMA_SMCR & ~0x07) | (n & 7) //ʱ//ģʽѡ
+#define PWMB_SMCR_SMS(n) PWMB_SMCR = (PWMB_SMCR & ~0x07) | (n & 7) //ʱ//ģʽѡ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_ETR = 0xFEC3H; ETP1 ECE1 ETPS11 ETPS10 ETF13 ETF12 ETF11 ETF10 0000,0000 /* ⲿĴ */
+//sfr PWMB_ETR = 0xFEE3H; ETP2 ECE2 ETPS21 ETPS20 ETF23 ETF22 ETF21 ETF20 0000,0000 /* ⲿĴ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_IER = 0xFEC4H; BIEA TIEA COMIEA CC4IE CC3IE CC2IE CC1IE UIEA 0000,0000 /* жʹܼĴ */
+//sfr PWMB_IER = 0xFEE4H; BIEB TIEB COMIEB CC8IE CC7IE CC6IE CC5IE UIEB 0000,0000 /* жʹܼĴ */
+#define PWMA_UIEA_Enable() PWMA_IER |= 0x01 //1ж
+#define PWMA_UIEA_Disable() PWMA_IER &= ~0x01 //0ֹж
+#define PWMA_CC1IE_Enable() PWMA_IER |= 0x02 //1/Ƚж
+#define PWMA_CC1IE_Disable() PWMA_IER &= ~0x02 //0ֹ/Ƚж
+#define PWMA_CC2IE_Enable() PWMA_IER |= 0x04 //1/Ƚж
+#define PWMA_CC2IE_Disable() PWMA_IER &= ~0x04 //0ֹ/Ƚж
+#define PWMA_CC3IE_Enable() PWMA_IER |= 0x08 //1/Ƚж
+#define PWMA_CC3IE_Disable() PWMA_IER &= ~0x08 //0ֹ/Ƚж
+#define PWMA_CC4IE_Enable() PWMA_IER |= 0x10 //1/Ƚж
+#define PWMA_CC4IE_Disable() PWMA_IER &= ~0x10 //0ֹ/Ƚж
+#define PWMA_COMIEA_Enable() PWMA_IER |= 0x20 //1COMж
+#define PWMA_COMIEA_Disable() PWMA_IER &= ~0x20 //0ֹCOMж
+#define PWMA_TIEA_Enable() PWMA_IER |= 0x40 //1ж
+#define PWMA_TIEA_Disable() PWMA_IER &= ~0x40 //0ֹж
+#define PWMA_BIEA_Enable() PWMA_IER |= 0x80 //1ɲж
+#define PWMA_BIEA_Disable() PWMA_IER &= ~0x80 //0ֹɲж
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_SR1 = 0xFEC5H; BIF1 TIF1 COMIF1 CC4IF CC3IF CC2IF CC1IF UIF1 0000,0000 /* ״̬Ĵ 1 */
+//sfr PWMB_SR1 = 0xFEE5H; BIF2 TIF2 COMIF2 CC8IF CC7IF CC6IF CC5IF UIF2 0000,0000 /* ״̬Ĵ 1 */
+#define UIF1 1
+#define CC1IF (1<<1)
+#define CC2IF (1<<2)
+#define CC3IF (1<<3)
+#define CC4IF (1<<4)
+#define COMIF1 (1<<5)
+#define TIF1 (1<<6)
+#define BIF1 (1<<7)
+
+#define UIF2 1
+#define CC5IF (1<<1)
+#define CC6IF (1<<2)
+#define CC7IF (1<<3)
+#define CC8IF (1<<4)
+#define COMIF2 (1<<5)
+#define TIF2 (1<<6)
+#define BIF2 (1<<7)
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_SR2 = 0xFEC6H; - - - CC4OF CC3OF CC2OF CC1OF - xxx0,000x /* ״̬Ĵ 2 */
+//sfr PWMB_SR2 = 0xFEE6H; - - - CC8OF CC7OF CC6OF CC5OF - xxx0,000x /* ״̬Ĵ 2 */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_EGR = 0xFEC7H; BG1 TG1 COMG1 CC4G CC3G CC2G CC1G UG1 0000,0000 /* ¼Ĵ */
+//sfr PWMB_EGR = 0xFEE7H; BG2 TG2 COMG2 CC8G CC7G CC6G CC5G UG2 0000,0000 /* ¼Ĵ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR1 = 0xFEC8H; OC1CE OC1M2 OC1M1 OC1M0 OC1PE OC1FE CC1S1 CC1S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪȽģʽ */
+//sfr PWMB_CCMR1 = 0xFEE8H; OC5CE OC5M2 OC5M1 OC5M0 OC5PE OC5FE CC5S1 CC5S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪȽģʽ */
+#define OCnCE (1<<7)
+
+#define CCMRn_FREEZE 0x00 //
+#define CCMRn_MATCH_VALID 0x10 //ƥʱͨ n ΪЧƽ
+#define CCMRn_MATCH_INVALID 0x20 //ƥʱͨ n ΪЧƽ
+#define CCMRn_ROLLOVER 0x30 //ת
+#define CCMRn_FORCE_INVALID 0x40 //ǿΪЧƽ
+#define CCMRn_FORCE_VALID 0x50 //ǿΪЧƽ
+#define CCMRn_PWM_MODE1 0x60 //PWM ģʽ 1
+#define CCMRn_PWM_MODE2 0x70 //PWM ģʽ 2
+
+#define PWMA_OC1ModeSet(n) PWMA_CCMR1 = (PWMA_CCMR1 & ~0x70) | (n) //Ƚģʽ
+#define PWMB_OC5ModeSet(n) PWMB_CCMR1 = (PWMB_CCMR1 & ~0x70) | (n) //Ƚģʽ
+
+#define PWMA_OC1_ReloadEnable() PWMA_CCMR1 |= 0x08 //1 OC1PE ȽϵԤװع
+#define PWMA_OC1_RelosdDisable() PWMA_CCMR1 &= ~0x08 //0ֹ OC1PE ȽϵԤװع
+#define PWMB_OC5_ReloadEnable() PWMB_CCMR1 |= 0x08 //1 OC5PE ȽϵԤװع
+#define PWMB_OC5_RelosdDisable() PWMB_CCMR1 &= ~0x08 //0ֹ OC5PE ȽϵԤװع
+
+#define PWMA_OC1_FastEnable() PWMA_CCMR1 |= 0x04 //1 OC1FE ȽϿٹ
+#define PWMA_OC1_FastDisable() PWMA_CCMR1 &= ~0x04 //0ֹ OC1FE ȽϿٹ
+#define PWMB_OC5_FastEnable() PWMB_CCMR1 |= 0x04 //1 OC5FE ȽϿٹ
+#define PWMB_OC5_FastDisable() PWMB_CCMR1 &= ~0x04 //0ֹ OC5FE ȽϿٹ
+
+#define CCAS_OUTPUT 0x00 //
+#define CCAS_IUTPUT_TI1FP1 0x01 //룬IC1/IC2/IC3/IC4 ӳ TI1FP1
+#define CCAS_IUTPUT_TI2FP1 0x02 //룬IC1/IC2/IC3/IC4 ӳ TI2FP1
+#define CCAS_IUTPUT_TRC 0x03 //룬IC1/IC2/IC3/IC4 ӳ TRC
+#define CCBS_OUTPUT 0x00 //
+#define CCBS_IUTPUT_TI5FP5 0x01 //룬IC5/IC6/IC7/IC8 ӳ TI5FP5
+#define CCBS_IUTPUT_TI6FP5 0x02 //룬IC5/IC6/IC7/IC8 ӳ TI6FP5
+#define CCBS_IUTPUT_TRC 0x03 //룬IC5/IC6/IC7/IC8 ӳ TRC
+
+#define PWMA_CC1S_Direction(n) PWMA_CCMR1 = (PWMA_CCMR1 & ~0x03) | (n) ///Ƚ 1 ѡλͨķ/ŵѡ
+#define PWMB_CC5S_Direction(n) PWMB_CCMR1 = (PWMB_CCMR1 & ~0x03) | (n) ///Ƚ 5 ѡλͨķ/ŵѡ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR1 = 0xFEC8H; IC1F3 IC1F2 IC1F1 IC1F0 IC1PSC1 IC1PSC0 CC1S1 CC1S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪģʽ */
+//sfr PWMB_CCMR1 = 0xFEE8H; IC5F3 IC5F2 IC5F1 IC5F0 IC5PSC1 IC5PSC0 CC5S1 CC5S0 0000,0000 /* /ȽģʽĴ 1 - ͨΪģʽ */
+
+#define ICnF_01_Clock 0
+#define ICnF_02_Clock 1
+#define ICnF_04_Clock 2
+#define ICnF_08_Clock 3
+#define ICnF_12_Clock 4
+#define ICnF_16_Clock 5
+#define ICnF_24_Clock 6
+#define ICnF_32_Clock 7
+#define ICnF_48_Clock 8
+#define ICnF_64_Clock 9
+#define ICnF_80_Clock 10
+#define ICnF_96_Clock 11
+#define ICnF_128_Clock 12
+#define ICnF_160_Clock 13
+#define ICnF_192_Clock 14
+#define ICnF_256_Clock 15
+
+#define PWMA_IC1F_FilterClock(n) PWMA_CCMR1 = (PWMA_CCMR1 & 0x0F) | (n<<4) //벶 1 ˲ѡλ TIn IJƵʼ˲
+#define PWMB_IC5F_FilterClock(n) PWMB_CCMR1 = (PWMB_CCMR1 & 0x0F) | (n<<4) //벶 5 ˲ѡλ TIn IJƵʼ˲
+
+#define PWMA_IC1PSC_PrescalerSet(n) PWMA_CCMR1 = (PWMA_CCMR1 & 0xF3) | ((n&3)<<2) /// 1 ԤƵ0~3
+#define PWMB_IC5PSC_PrescalerSet(n) PWMB_CCMR1 = (PWMB_CCMR1 & 0xF3) | ((n&3)<<2) /// 5 ԤƵ0~3
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR2 = 0xFEC9H; OC2CE OC2M2 OC2M1 OC2M0 OC2PE OC2FE CC2S1 CC2S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪȽģʽ */
+//sfr PWMB_CCMR2 = 0xFEE9H; OC6CE OC6M2 OC6M1 OC6M0 OC6PE OC6FE CC6S1 CC6S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪȽģʽ */
+
+#define PWMA_OC2ModeSet(n) PWMA_CCMR2 = (PWMA_CCMR2 & ~0x70) | (n) //Ƚģʽ
+#define PWMB_OC6ModeSet(n) PWMB_CCMR2 = (PWMB_CCMR2 & ~0x70) | (n) //Ƚģʽ
+
+#define PWMA_OC2_ReloadEnable() PWMA_CCMR2 |= 0x08 //1 OC2PE ȽϵԤװع
+#define PWMA_OC2_RelosdDisable() PWMA_CCMR2 &= ~0x08 //0ֹ OC2PE ȽϵԤװع
+#define PWMB_OC6_ReloadEnable() PWMB_CCMR2 |= 0x08 //1 OC6PE ȽϵԤװع
+#define PWMB_OC6_RelosdDisable() PWMB_CCMR2 &= ~0x08 //0ֹ OC6PE ȽϵԤװع
+
+#define PWMA_OC2_FastEnable() PWMA_CCMR2 |= 0x04 //1 OC2FE ȽϿٹ
+#define PWMA_OC2_FastDisable() PWMA_CCMR2 &= ~0x04 //0ֹ OC2FE ȽϿٹ
+#define PWMB_OC6_FastEnable() PWMB_CCMR2 |= 0x04 //1 OC6FE ȽϿٹ
+#define PWMB_OC6_FastDisable() PWMB_CCMR2 &= ~0x04 //0ֹ OC6FE ȽϿٹ
+
+#define PWMA_CC2S_Direction(n) PWMA_CCMR2 = (PWMA_CCMR2 & ~0x03) | (n) ///Ƚ 2 ѡλͨķ/ŵѡ
+#define PWMB_CC6S_Direction(n) PWMB_CCMR2 = (PWMB_CCMR2 & ~0x03) | (n) ///Ƚ 6 ѡλͨķ/ŵѡ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR2 = 0xFEC9H; IC2F3 IC2F2 IC2F1 IC2F0 IC2PSC1 IC2PSC0 CC2S1 CC2S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪģʽ */
+//sfr PWMB_CCMR2 = 0xFEE9H; IC6F3 IC6F2 IC6F1 IC6F0 IC6PSC1 IC6PSC0 CC6S1 CC6S0 0000,0000 /* /ȽģʽĴ 2 - ͨΪģʽ */
+
+#define PWMA_IC2F_FilterClock(n) PWMA_CCMR2 = (PWMA_CCMR2 & 0x0F) | (n<<4) //벶 2 ˲ѡλ TIn IJƵʼ˲
+#define PWMB_IC6F_FilterClock(n) PWMB_CCMR2 = (PWMB_CCMR2 & 0x0F) | (n<<4) //벶 6 ˲ѡλ TIn IJƵʼ˲
+
+#define PWMA_IC2PSC_PrescalerSet(n) PWMA_CCMR2 = (PWMA_CCMR2 & 0xF3) | ((n&3)<<2) /// 2 ԤƵ0~3
+#define PWMB_IC6PSC_PrescalerSet(n) PWMB_CCMR2 = (PWMB_CCMR2 & 0xF3) | ((n&3)<<2) /// 6 ԤƵ0~3
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR3 = 0xFECAH; OC3CE OC3M2 OC3M1 OC3M0 OC3PE OC3FE CC3S1 CC3S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪȽģʽ */
+//sfr PWMB_CCMR3 = 0xFEEAH; OC7CE OC7M2 OC7M1 OC7M0 OC7PE OC7FE CC7S1 CC7S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪȽģʽ */
+
+#define PWMA_OC3ModeSet(n) PWMA_CCMR3 = (PWMA_CCMR3 & ~0x70) | (n) //Ƚģʽ
+#define PWMB_OC7ModeSet(n) PWMB_CCMR3 = (PWMB_CCMR3 & ~0x70) | (n) //Ƚģʽ
+
+#define PWMA_OC3_ReloadEnable() PWMA_CCMR3 |= 0x08 //1 OC3PE ȽϵԤװع
+#define PWMA_OC3_RelosdDisable() PWMA_CCMR3 &= ~0x08 //0ֹ OC3PE ȽϵԤװع
+#define PWMB_OC7_ReloadEnable() PWMB_CCMR3 |= 0x08 //1 OC7PE ȽϵԤװع
+#define PWMB_OC7_RelosdDisable() PWMB_CCMR3 &= ~0x08 //0ֹ OC7PE ȽϵԤװع
+
+#define PWMA_OC3_FastEnable() PWMA_CCMR3 |= 0x04 //1 OC3FE ȽϿٹ
+#define PWMA_OC3_FastDisable() PWMA_CCMR3 &= ~0x04 //0ֹ OC3FE ȽϿٹ
+#define PWMB_OC7_FastEnable() PWMB_CCMR3 |= 0x04 //1 OC7FE ȽϿٹ
+#define PWMB_OC7_FastDisable() PWMB_CCMR3 &= ~0x04 //0ֹ OC7FE ȽϿٹ
+
+#define PWMA_CC3S_Direction(n) PWMA_CCMR3 = (PWMA_CCMR3 & ~0x03) | (n) ///Ƚ 3 ѡλͨķ/ŵѡ
+#define PWMB_CC7S_Direction(n) PWMB_CCMR3 = (PWMB_CCMR3 & ~0x03) | (n) ///Ƚ 7 ѡλͨķ/ŵѡ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR3 = 0xFECAH; IC3F3 IC3F2 IC3F1 IC3F0 IC3PSC1 IC3PSC0 CC3S1 CC3S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪģʽ */
+//sfr PWMB_CCMR3 = 0xFEEAH; IC7F3 IC7F2 IC7F1 IC7F0 IC7PSC1 IC7PSC0 CC7S1 CC7S0 0000,0000 /* /ȽģʽĴ 3 - ͨΪģʽ */
+
+#define PWMA_IC3F_FilterClock(n) PWMA_CCMR3 = (PWMA_CCMR3 & 0x0F) | (n<<4) //벶 3 ˲ѡλ TIn IJƵʼ˲
+#define PWMB_IC7F_FilterClock(n) PWMB_CCMR3 = (PWMB_CCMR3 & 0x0F) | (n<<4) //벶 7 ˲ѡλ TIn IJƵʼ˲
+
+#define PWMA_IC3PSC_PrescalerSet(n) PWMA_CCMR3 = (PWMA_CCMR3 & 0xF3) | ((n&3)<<2) /// 3 ԤƵ0~3
+#define PWMB_IC7PSC_PrescalerSet(n) PWMB_CCMR3 = (PWMB_CCMR3 & 0xF3) | ((n&3)<<2) /// 7 ԤƵ0~3
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR4 = 0xFECBH; OC4CE OC4M2 OC4M1 OC4M0 OC4PE OC4FE CC4S1 CC4S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪȽģʽ */
+//sfr PWMB_CCMR4 = 0xFEEBH; OC8CE OC8M2 OC8M1 OC8M0 OC8PE OC8FE CC8S1 CC8S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪȽģʽ */
+
+#define PWMA_OC4ModeSet(n) PWMA_CCMR4 = (PWMA_CCMR4 & ~0x70) | (n) //Ƚģʽ
+#define PWMB_OC8ModeSet(n) PWMB_CCMR4 = (PWMB_CCMR4 & ~0x70) | (n) //Ƚģʽ
+
+#define PWMA_OC4_ReloadEnable() PWMA_CCMR4 |= 0x08 //1 OC4PE ȽϵԤװع
+#define PWMA_OC4_RelosdDisable() PWMA_CCMR4 &= ~0x08 //0ֹ OC4PE ȽϵԤװع
+#define PWMB_OC8_ReloadEnable() PWMB_CCMR4 |= 0x08 //1 OC8PE ȽϵԤװع
+#define PWMB_OC8_RelosdDisable() PWMB_CCMR4 &= ~0x08 //0ֹ OC8PE ȽϵԤװع
+
+#define PWMA_OC4_FastEnable() PWMA_CCMR4 |= 0x04 //1 OC4FE ȽϿٹ
+#define PWMA_OC4_FastDisable() PWMA_CCMR4 &= ~0x04 //0ֹ OC4FE ȽϿٹ
+#define PWMB_OC8_FastEnable() PWMB_CCMR4 |= 0x04 //1 OC8FE ȽϿٹ
+#define PWMB_OC8_FastDisable() PWMB_CCMR4 &= ~0x04 //0ֹ OC8FE ȽϿٹ
+
+#define PWMA_CC4S_Direction(n) PWMA_CCMR4 = (PWMA_CCMR4 & ~0x03) | (n) ///Ƚ 4 ѡλͨķ/ŵѡ
+#define PWMB_CC8S_Direction(n) PWMB_CCMR4 = (PWMB_CCMR4 & ~0x03) | (n) ///Ƚ 8 ѡλͨķ/ŵѡ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCMR4 = 0xFECBH; IC4F3 IC4F2 IC4F1 IC4F0 IC4PSC1 IC4PSC0 CC4S1 CC4S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪģʽ */
+//sfr PWMB_CCMR4 = 0xFEEBH; IC8F3 IC8F2 IC8F1 IC8F0 IC8PSC1 IC8PSC0 CC8S1 CC8S0 0000,0000 /* /ȽģʽĴ 4 - ͨΪģʽ */
+
+#define PWMA_IC4F_FilterClock(n) PWMA_CCMR4 = (PWMA_CCMR4 & 0x0F) | (n<<4) //벶 4 ˲ѡλ TIn IJƵʼ˲
+#define PWMB_IC8F_FilterClock(n) PWMB_CCMR4 = (PWMB_CCMR4 & 0x0F) | (n<<4) //벶 8 ˲ѡλ TIn IJƵʼ˲
+
+#define PWMA_IC4PSC_PrescalerSet(n) PWMA_CCMR4 = (PWMA_CCMR4 & 0xF3) | ((n&3)<<2) /// 4 ԤƵ0~3
+#define PWMB_IC8PSC_PrescalerSet(n) PWMB_CCMR4 = (PWMB_CCMR4 & 0xF3) | ((n&3)<<2) /// 8 ԤƵ0~3
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCER1 = 0xFECCH; CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E 0000,0000 /* /ȽʹܼĴ 1 */
+//sfr PWMB_CCER1 = 0xFEECH; - - CC6P CC6E - - CC5P CC5E 0000,0000 /* /ȽʹܼĴ 1 */
+
+#define PWMA_CCER1_Disable() PWMA_CCER1 = 0x00 //ر벶/Ƚ
+#define PWMA_CC1E_Enable() PWMA_CCER1 |= 0x01 //1벶/Ƚ
+#define PWMA_CC1E_Disable() PWMA_CCER1 &= ~0x01 //0ر벶/Ƚ
+#define PWMA_CC1P_LowValid() PWMA_CCER1 |= 0x02 //1͵ƽЧ
+#define PWMA_CC1P_HighValid() PWMA_CCER1 &= ~0x02 //0ߵƽЧ
+#define PWMA_CC1P_CaptureRise() PWMA_CCER1 |= 0x02 //1 TI1F TI2F ½
+#define PWMA_CC1P_CaptureFall() PWMA_CCER1 &= ~0x02 //0 TI1F TI2F
+#define PWMA_CC1NE_Enable() PWMA_CCER1 |= 0x04 //1Ƚ
+#define PWMA_CC1NE_Disable() PWMA_CCER1 &= ~0x04 //0رձȽ
+#define PWMA_CC1NP_LowValid() PWMA_CCER1 |= 0x08 //1͵ƽЧ
+#define PWMA_CC1NP_HighValid() PWMA_CCER1 &= ~0x08 //0ߵƽЧ
+
+#define PWMA_CC2E_Enable() PWMA_CCER1 |= 0x10 //1벶/Ƚ
+#define PWMA_CC2E_Disable() PWMA_CCER1 &= ~0x10 //0ر벶/Ƚ
+#define PWMA_CC2P_LowValid() PWMA_CCER1 |= 0x20 //1͵ƽЧ
+#define PWMA_CC2P_HighValid() PWMA_CCER1 &= ~0x20 //0ߵƽЧ
+#define PWMA_CC2P_CaptureRise() PWMA_CCER1 |= 0x20 //1 TI1F TI2F ½
+#define PWMA_CC2P_CaptureFall() PWMA_CCER1 &= ~0x20 //0 TI1F TI2F
+#define PWMA_CC2NE_Enable() PWMA_CCER1 |= 0x40 //1Ƚ
+#define PWMA_CC2NE_Disable() PWMA_CCER1 &= ~0x40 //0رձȽ
+#define PWMA_CC2NP_LowValid() PWMA_CCER1 |= 0x80 //1͵ƽЧ
+#define PWMA_CC2NP_HighValid() PWMA_CCER1 &= ~0x80 //0ߵƽЧ
+
+#define PWMB_CCER1_Disable() PWMB_CCER1 = 0x00 //ر벶/Ƚ
+#define PWMB_CC5E_Enable() PWMB_CCER1 |= 0x01 //1벶/Ƚ
+#define PWMB_CC5E_Disable() PWMB_CCER1 &= ~0x01 //0ر벶/Ƚ
+#define PWMB_CC5P_LowValid() PWMB_CCER1 |= 0x02 //1͵ƽЧ
+#define PWMB_CC5P_HighValid() PWMB_CCER1 &= ~0x02 //0ߵƽЧ
+#define PWMB_CC5P_CaptureRise() PWMB_CCER1 |= 0x02 //1 TI1F TI2F ½
+#define PWMB_CC5P_CaptureFall() PWMB_CCER1 &= ~0x02 //0 TI1F TI2F
+
+#define PWMB_CC6E_Enable() PWMB_CCER1 |= 0x10 //1벶/Ƚ
+#define PWMB_CC6E_Disable() PWMB_CCER1 &= ~0x10 //0ر벶/Ƚ
+#define PWMB_CC6P_LowValid() PWMB_CCER1 |= 0x20 //1͵ƽЧ
+#define PWMB_CC6P_HighValid() PWMB_CCER1 &= ~0x20 //0ߵƽЧ
+#define PWMB_CC6P_CaptureRise() PWMB_CCER1 |= 0x20 //1 TI1F TI2F ½
+#define PWMB_CC6P_CaptureFall() PWMB_CCER1 &= ~0x20 //0 TI1F TI2F
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCER2 = 0xFECDH; CC4NP CC4NE CC4P CC4E CC3NP CC3NE CC3P CC3E 0000,0000 /* /ȽʹܼĴ 2 */
+//sfr PWMB_CCER2 = 0xFEEDH; - - CC8P CC8E - - CC7P CC7E 0000,0000 /* /ȽʹܼĴ 2 */
+
+#define PWMA_CCER2_Disable() PWMA_CCER2 = 0x00 //ر벶/Ƚ
+#define PWMA_CC3E_Enable() PWMA_CCER2 |= 0x01 //1벶/Ƚ
+#define PWMA_CC3E_Disable() PWMA_CCER2 &= ~0x01 //0ر벶/Ƚ
+#define PWMA_CC3P_LowValid() PWMA_CCER2 |= 0x02 //1͵ƽЧ
+#define PWMA_CC3P_HighValid() PWMA_CCER2 &= ~0x02 //0ߵƽЧ
+#define PWMA_CC3P_CaptureRise() PWMA_CCER2 |= 0x02 //1 TI1F TI2F ½
+#define PWMA_CC3P_CaptureFall() PWMA_CCER2 &= ~0x02 //0 TI1F TI2F
+#define PWMA_CC3NE_Enable() PWMA_CCER2 |= 0x04 //1Ƚ
+#define PWMA_CC3NE_Disable() PWMA_CCER2 &= ~0x04 //0رձȽ
+#define PWMA_CC3NP_LowValid() PWMA_CCER2 |= 0x08 //1͵ƽЧ
+#define PWMA_CC3NP_HighValid() PWMA_CCER2 &= ~0x08 //0ߵƽЧ
+
+#define PWMA_CC4E_Enable() PWMA_CCER2 |= 0x10 //1벶/Ƚ
+#define PWMA_CC4E_Disable() PWMA_CCER2 &= ~0x10 //0ر벶/Ƚ
+#define PWMA_CC4P_LowValid() PWMA_CCER2 |= 0x20 //1͵ƽЧ
+#define PWMA_CC4P_HighValid() PWMA_CCER2 &= ~0x20 //0ߵƽЧ
+#define PWMA_CC4P_CaptureRise() PWMA_CCER2 |= 0x20 //1 TI1F TI2F ½
+#define PWMA_CC4P_CaptureFall() PWMA_CCER2 &= ~0x20 //0 TI1F TI2F
+#define PWMA_CC4NE_Enable() PWMA_CCER2 |= 0x40 //1Ƚ
+#define PWMA_CC4NE_Disable() PWMA_CCER2 &= ~0x40 //0رձȽ
+#define PWMA_CC4NP_LowValid() PWMA_CCER2 |= 0x80 //1͵ƽЧ
+#define PWMA_CC4NP_HighValid() PWMA_CCER2 &= ~0x80 //0ߵƽЧ
+
+#define PWMB_CCER2_Disable() PWMB_CCER2 = 0x00 //ر벶/Ƚ
+#define PWMB_CC7E_Enable() PWMB_CCER2 |= 0x01 //1벶/Ƚ
+#define PWMB_CC7E_Disable() PWMB_CCER2 &= ~0x01 //0ر벶/Ƚ
+#define PWMB_CC7P_LowValid() PWMB_CCER2 |= 0x02 //1͵ƽЧ
+#define PWMB_CC7P_HighValid() PWMB_CCER2 &= ~0x02 //0ߵƽЧ
+#define PWMB_CC7P_CaptureRise() PWMB_CCER2 |= 0x02 //1 TI1F TI2F ½
+#define PWMB_CC7P_CaptureFall() PWMB_CCER2 &= ~0x02 //0 TI1F TI2F
+
+#define PWMB_CC8E_Enable() PWMB_CCER2 |= 0x10 //1벶/Ƚ
+#define PWMB_CC8E_Disable() PWMB_CCER2 &= ~0x10 //0ر벶/Ƚ
+#define PWMB_CC8P_LowValid() PWMB_CCER2 |= 0x20 //1͵ƽЧ
+#define PWMB_CC8P_HighValid() PWMB_CCER2 &= ~0x20 //0ߵƽЧ
+#define PWMB_CC8P_CaptureRise() PWMB_CCER2 |= 0x20 //1 TI1F TI2F ½
+#define PWMB_CC8P_CaptureFall() PWMB_CCER2 &= ~0x20 //0 TI1F TI2F
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CNTRH = 0xFECEH; CNT1[15:8] 0000,0000 /* 8 λ */
+//sfr PWMB_CNTRH = 0xFEEEH; CNT2[15:8] 0000,0000 /* 8 λ */
+//sfr PWMA_CNTRL = 0xFECFH; CNT1[7:0] 0000,0000 /* 8 λ */
+//sfr PWMB_CNTRL = 0xFEEFH; CNT2[7:0] 0000,0000 /* 8 λ */
+
+#define PWMA_Counter(n) PWMA_CNTR = n //
+#define PWMB_Counter(n) PWMB_CNTR = n //
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_PSCRH = 0xFED0H; PSC1[15:8] 0000,0000 /* ԤƵ 8 λ */
+//sfr PWMB_PSCRH = 0xFEF0H; PSC2[15:8] 0000,0000 /* ԤƵ 8 λ */
+//sfr PWMA_PSCRL = 0xFED1H; PSC1[7:0] 0000,0000 /* ԤƵ 8 λ */
+//sfr PWMB_PSCRL = 0xFEF1H; PSC2[7:0] 0000,0000 /* ԤƵ 8 λ */
+
+#define PWMA_Prescaler(n) PWMA_PSCR = n //ԤƵ
+#define PWMB_Prescaler(n) PWMB_PSCR = n //ԤƵ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_ARRH = 0xFED2H; ARR1[15:8] 0000,0000 /* ԶװؼĴ 8 λ */
+//sfr PWMB_ARRH = 0xFEF2H; ARR2[15:8] 0000,0000 /* ԶװؼĴ 8 λ */
+//sfr PWMA_ARRL = 0xFED3H; ARR1[7:0] 0000,0000 /* ԶװؼĴ 8 λ */
+//sfr PWMB_ARRL = 0xFEF3H; ARR2[7:0] 0000,0000 /* ԶװؼĴ 8 λ */
+
+#define PWMA_AutoReload(n) PWMA_ARR = n //ԶװؼĴ
+#define PWMB_AutoReload(n) PWMB_ARR = n //ԶװؼĴ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_RCR = 0xFED4H; REP1[7:0] 0000,0000 /* ظĴ */
+//sfr PWMB_RCR = 0xFEF4H; REP2[7:0] 0000,0000 /* ظĴ */
+
+#define PWMA_ReCounter(n) PWMA_RCR = n //ظĴ
+#define PWMB_ReCounter(n) PWMB_RCR = n //ظĴ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCR1H = 0xFED5H; CCR1[15:8] 0000,0000 /* /ȽϼĴ 1 8 λ */
+//sfr PWMB_CCR5H = 0xFEF5H; CCR5[15:8] 0000,0000 /* /ȽϼĴ 1 8 λ */
+//sfr PWMA_CCR1L = 0xFED6H; CCR1[7:0] 0000,0000 /* /ȽϼĴ 1 8 λ */
+//sfr PWMB_CCR5L = 0xFEF6H; CCR5[7:0] 0000,0000 /* /ȽϼĴ 1 8 λ */
+
+#define PWMA_Duty1(n) PWMA_CCR1 = n ///ȽϼĴ 1
+#define PWMB_Duty5(n) PWMB_CCR5 = n ///ȽϼĴ 1
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCR2H = 0xFED7H; CCR2[15:8] 0000,0000 /* /ȽϼĴ 2 8 λ */
+//sfr PWMB_CCR6H = 0xFEF7H; CCR6[15:8] 0000,0000 /* /ȽϼĴ 2 8 λ */
+//sfr PWMA_CCR2L = 0xFED8H; CCR2[7:0] 0000,0000 /* /ȽϼĴ 2 8 λ */
+//sfr PWMB_CCR6L = 0xFEF8H; CCR6[7:0] 0000,0000 /* /ȽϼĴ 2 8 λ */
+
+#define PWMA_Duty2(n) PWMA_CCR2 = n ///ȽϼĴ 2
+#define PWMB_Duty6(n) PWMB_CCR6 = n ///ȽϼĴ 2
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCR3H = 0xFED9H; CCR3[15:8] 0000,0000 /* /ȽϼĴ 3 8 λ */
+//sfr PWMB_CCR7H = 0xFEF9H; CCR7[15:8] 0000,0000 /* /ȽϼĴ 3 8 λ */
+//sfr PWMA_CCR3L = 0xFEDAH; CCR3[7:0] 0000,0000 /* /ȽϼĴ 3 8 λ */
+//sfr PWMB_CCR7L = 0xFEFAH; CCR7[7:0] 0000,0000 /* /ȽϼĴ 3 8 λ */
+
+#define PWMA_Duty3(n) PWMA_CCR3 = n ///ȽϼĴ 3
+#define PWMB_Duty7(n) PWMB_CCR7 = n ///ȽϼĴ 3
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_CCR4H = 0xFEDBH; CCR4[15:8] 0000,0000 /* /ȽϼĴ 4 8 λ */
+//sfr PWMB_CCR8H = 0xFEFBH; CCR8[15:8] 0000,0000 /* /ȽϼĴ 4 8 λ */
+//sfr PWMA_CCR4L = 0xFEDCH; CCR4[7:0] 0000,0000 /* /ȽϼĴ 4 8 λ */
+//sfr PWMB_CCR8L = 0xFEFCH; CCR8[7:0] 0000,0000 /* /ȽϼĴ 4 8 λ */
+
+#define PWMA_Duty4(n) PWMA_CCR4 = n ///ȽϼĴ 4
+#define PWMB_Duty8(n) PWMB_CCR8 = n ///ȽϼĴ 4
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_BRK = 0xFEDDH; MOE1 AOE1 BKP1 BKE1 OSSR1 OSSI1 LOCK11 LOCK10 0000,0000 /* ɲĴ */
+//sfr PWMB_BRK = 0xFEFDH; MOE2 AOE2 BKP2 BKE2 OSSR2 OSSI2 LOCK21 LOCK20 0000,0000 /* ɲĴ */
+
+#define PWMA_BrakeOutputEnable() PWMA_BRK |= 0x80 //1ʹ
+#define PWMA_BrakeOutputDisable() PWMA_BRK &= ~0x80 //0ֹ
+#define PWMB_BrakeOutputEnable() PWMB_BRK |= 0x80 //1ʹ
+#define PWMB_BrakeOutputDisable() PWMB_BRK &= ~0x80 //0ֹ
+
+#define PWMA_BrakeAutoOutputEnable() PWMA_BRK |= 0x40 //1Զʹ
+#define PWMA_BrakeAutoOutputDisable() PWMA_BRK &= ~0x40 //0Զֹ
+#define PWMB_BrakeAutoOutputEnable() PWMB_BRK |= 0x40 //1Զʹ
+#define PWMB_BrakeAutoOutputDisable() PWMB_BRK &= ~0x40 //0Զֹ
+
+#define PWMA_BrakeHighValid() PWMA_BRK |= 0x20 //1ɲߵƽЧ
+#define PWMA_BrakeLowValid() PWMA_BRK &= ~0x20 //0ɲ͵ƽЧ
+#define PWMB_BrakeHighValid() PWMB_BRK |= 0x20 //1ɲߵƽЧ
+#define PWMB_BrakeLowValid() PWMB_BRK &= ~0x20 //0ɲ͵ƽЧ
+
+#define PWMA_BrakeEnable() PWMA_BRK |= 0x10 //1ɲ
+#define PWMA_BrakeDisable() PWMA_BRK &= ~0x10 //0ֹɲ
+#define PWMB_BrakeEnable() PWMB_BRK |= 0x10 //1ɲ
+#define PWMB_BrakeDisable() PWMB_BRK &= ~0x10 //0ֹɲ
+
+//ģʽ¡ر״̬ѡ
+#define PWMA_OSSRnEnable() PWMA_BRK |= 0x08 //1 PWM ʱһ CCiE=1 CCiNE=1ȿ OC/OCN ЧƽȻOC/OCN ʹź=1
+#define PWMA_OSSRnDisable() PWMA_BRK &= ~0x08 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0
+#define PWMB_OSSRnEnable() PWMB_BRK |= 0x08 //1 PWM ʱһ CCiE=1 CCiNE=1ȿ OC/OCN ЧƽȻOC/OCN ʹź=1
+#define PWMB_OSSRnDisable() PWMB_BRK &= ~0x08 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0
+//ģʽ¡ر״̬ѡ
+#define PWMA_OSSInEnable() PWMA_BRK |= 0x04 //1 PWM ʱһ CCiE=1 CCiNE=1OC/OCN еƽȻ OC/OCNʹź=1
+#define PWMA_OSSInDisable() PWMA_BRK &= ~0x04 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0
+#define PWMB_OSSInEnable() PWMB_BRK |= 0x04 //1 PWM ʱһ CCiE=1 CCiNE=1OC/OCN еƽȻ OC/OCNʹź=1
+#define PWMB_OSSInDisable() PWMB_BRK &= ~0x04 //0 PWM ʱֹ OC/OCN OC/OCN ʹź=0
+
+#define PWMn_lock_L0 0 //Ĵд
+#define PWMn_lock_L1 1 // 1д PWMn_BKR Ĵ BKEBKPAOE λPWMn_OISR Ĵ OISI λ
+#define PWMn_lock_L2 2 // 2д 1 еĸλҲд CC λԼ OSSR/OSSI λ
+#define PWMn_lock_L3 3 // 3д 2 еĸλҲд CC λ
+
+#define PWMA_LockLevelSet(n) PWMA_BRK = (PWMA_BRK & ~0x03) | (n&3) //áλΪֹṩдʩ
+#define PWMB_LockLevelSet(n) PWMB_BRK = (PWMB_BRK & ~0x03) | (n&3) //áλΪֹṩдʩ
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_DTR = 0xFEDEH; DTG1[7:0] 0000,0000 /* Ĵ */
+//sfr PWMB_DTR = 0xFEFEH; DTG2[7:0] 0000,0000 /* Ĵ */
+
+//DTGn[7:5] = 000~011: ʱ = DTGn[7:0] * tCK_PSC
+//DTGn[7:5] = 100~101: ʱ = (64 + DTGn[6:0]) * 2 * tCK_PSC
+//DTGn[7:5] = 110: ʱ = (32 + DTGn[5:0]) * 8 * tCK_PSC
+//DTGn[7:5] = 111: ʱ = (32 + DTGn[4:0]) * 16 * tCK_PSC
+
+#define PWMA_DeadTime(n) PWMA_DTR = n //
+#define PWMB_DeadTime(n) PWMB_DTR = n //
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr PWMA_OISR = 0xFEDFH; OIS4N OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 0000,0000 /* ״̬Ĵ */
+//sfr PWMB_OISR = 0xFEFFH; - OIS8 - OIS7 - OIS6 - OIS5 x0x0,x0x0 /* ״̬Ĵ */
+
+#define PWMA_OC1_OUT_0() PWMA_OISR &= ~0x01 /* MOE=0 ʱ OC1N ʹܣһOC1=0 */
+#define PWMA_OC1_OUT_1() PWMA_OISR |= 0x01 /* MOE=0 ʱ OC1N ʹܣһOC1=1 */
+#define PWMA_OC1N_OUT_0() PWMA_OISR &= ~0x02 /* MOE=0 ʱһOC1N=0 */
+#define PWMA_OC1N_OUT_1() PWMA_OISR |= 0x02 /* MOE=0 ʱһOC1N=1 */
+#define PWMA_OC2_OUT_0() PWMA_OISR &= ~0x04 /* MOE=0 ʱ OC2N ʹܣһOC2=0 */
+#define PWMA_OC2_OUT_1() PWMA_OISR |= 0x04 /* MOE=0 ʱ OC2N ʹܣһOC2=1 */
+#define PWMA_OC2N_OUT_0() PWMA_OISR &= ~0x08 /* MOE=0 ʱһOC2N=0 */
+#define PWMA_OC2N_OUT_1() PWMA_OISR |= 0x08 /* MOE=0 ʱһOC2N=1 */
+#define PWMA_OC3_OUT_0() PWMA_OISR &= ~0x10 /* MOE=0 ʱ OC3N ʹܣһOC3=0 */
+#define PWMA_OC3_OUT_1() PWMA_OISR |= 0x10 /* MOE=0 ʱ OC3N ʹܣһOC3=1 */
+#define PWMA_OC3N_OUT_0() PWMA_OISR &= ~0x20 /* MOE=0 ʱһOC3N=0 */
+#define PWMA_OC3N_OUT_1() PWMA_OISR |= 0x20 /* MOE=0 ʱһOC3N=1 */
+#define PWMA_OC4_OUT_0() PWMA_OISR &= ~0x40 /* MOE=0 ʱ OC4N ʹܣһOC4=0 */
+#define PWMA_OC4_OUT_1() PWMA_OISR |= 0x40 /* MOE=0 ʱ OC4N ʹܣһOC4=1 */
+#define PWMA_OC4N_OUT_0() PWMA_OISR &= ~0x80 /* MOE=0 ʱһOC4N=0 */
+#define PWMA_OC4N_OUT_1() PWMA_OISR |= 0x80 /* MOE=0 ʱһOC4N=1 */
+
+#define PWMB_OC5_OUT_0() PWMB_OISR &= ~0x01 /* MOE=0 ʱһOC5=0 */
+#define PWMB_OC5_OUT_1() PWMB_OISR |= 0x01 /* MOE=0 ʱһOC5=1 */
+#define PWMB_OC6_OUT_0() PWMB_OISR &= ~0x04 /* MOE=0 ʱһOC6=0 */
+#define PWMB_OC6_OUT_1() PWMB_OISR |= 0x04 /* MOE=0 ʱһOC6=1 */
+#define PWMB_OC7_OUT_0() PWMB_OISR &= ~0x10 /* MOE=0 ʱһOC7=0 */
+#define PWMB_OC7_OUT_1() PWMB_OISR |= 0x10 /* MOE=0 ʱһOC7=1 */
+#define PWMB_OC8_OUT_0() PWMB_OISR &= ~0x40 /* MOE=0 ʱһOC8=0 */
+#define PWMB_OC8_OUT_1() PWMB_OISR |= 0x40 /* MOE=0 ʱһOC8=1 */
+
+
+
+
+/*
+;PCA_PWMn: 7 6 5 4 3 2 1 0
+; EBSn_1 EBSn_0 - - - - EPCnH EPCnL
+;B5-B2:
+;B1(EPCnH): PWMģʽ£CCAPnH9λ
+;B0(EPCnL): PWMģʽ£CCAPnL9λ
+*/
+#define PWM0_NORMAL() PCA_PWM0 &= ~3 /* PWM0(Ĭ) */
+#define PWM0_OUT_0() PCA_PWM0 |= 3, CCAP0H = 0xff /* PWM0һֱ0 */
+#define PWM0_OUT_1() PCA_PWM0 &= 0xc0, CCAP0H = 0 /* PWM0һֱ1 */
+
+#define PWM1_NORMAL() PCA_PWM1 &= ~3 /* PWM1(Ĭ) */
+#define PWM1_OUT_0() PCA_PWM1 |= 3, CCAP1H = 0xff /* PWM1һֱ0 */
+#define PWM1_OUT_1() PCA_PWM1 &= 0xc0, CCAP1H = 0 /* PWM1һֱ1 */
+
+#define PWM2_NORMAL() PCA_PWM2 &= ~3 /* PWM2(Ĭ) */
+#define PWM2_OUT_0() PCA_PWM2 |= 3, CCAP2H = 0xff /* PWM2һֱ0 */
+#define PWM2_OUT_1() PCA_PWM2 &= 0xc0, CCAP2H = 0 /* PWM2һֱ1 */
+
+//#define PWM3_NORMAL() PCA_PWM3 &= ~3 /* PWM3(Ĭ) */
+//#define PWM3_OUT_0() PCA_PWM3 |= 3, CCAP3H = 0xff /* PWM3һֱ0 */
+//#define PWM3_OUT_1() PCA_PWM3 &= 0xc0, CCAP3H = 0 /* PWM3һֱ1 */
+
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr CCON = 0xD8; CF CR - - CCF3 CCF2 CCF1 CCF0 00xx,xx00 //PCA ƼĴ
+sbit CCF0 = CCON^0; /* PCA ģ0жϱ־Ӳλ0 */
+sbit CCF1 = CCON^1; /* PCA ģ1жϱ־Ӳλ0 */
+sbit CCF2 = CCON^2; /* PCA ģ2жϱ־Ӳλ0 */
+//sbit CCF3 = CCON^3; /* PCA ģ3жϱ־Ӳλ0 */
+sbit CR = CCON^6; /* 1: PCA0*/
+sbit CF = CCON^7; /* PCACHCLFFFFHΪ0000H־PCAӲλ0*/
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr CMOD = 0xD9; CIDL - - - CPS2 CPS1 CPS0 ECF 0xxx,0000 //PCA ģʽĴ
+#define PCA_IDLE_OFF() CMOD |= (1<<7) /* IDLE״̬PCAֹͣ */
+#define PCA_IDLE_ON() CMOD &= ~(1<<7) /* IDLE״̬PCA */
+#define PCA_CLK_12T() CMOD &= ~0x0E /* PCAѡ fosc/12 */
+#define PCA_CLK_2T() CMOD = (CMOD & ~0x0E) + 2 /* PCAѡ fosc/2 */
+#define PCA_CLK_T0() CMOD = (CMOD & ~0x0E) + 4 /* PCAѡTimer0жϣTimer0ͨAUXRĴóɹ12T1Tģʽ */
+#define PCA_CLK_ECI() CMOD = (CMOD & ~0x0E) + 6 /* PCAѡECI/P3.4ⲿʱӣ fosc/2 */
+#define PCA_CLK_1T() CMOD = (CMOD & ~0x0E) + 8 /* PCAѡ Fosc */
+#define PCA_CLK_4T() CMOD = (CMOD & ~0x0E) + 10 /* PCAѡ Fosc/4 */
+#define PCA_CLK_6T() CMOD = (CMOD & ~0x0E) + 12 /* PCAѡ Fosc/6 */
+#define PCA_CLK_8T() CMOD = (CMOD & ~0x0E) + 14 /* PCAѡ Fosc/8 */
+#define PCA_INT_ENABLE() CMOD |= 1 /* PCAжλ1---CFCCON.7жϡ */
+#define PCA_INT_DISABLE() CMOD &= ~1 /* PCAжϽֹ */
+
+// 7 6 5 4 3 2 1 0 Reset Value
+//sfr P_SW1 = 0xA2; S1_S1 S1_S0 CCP_S1 CCP_S0 SPI_S1 SPI_S0 0 - nn00,000x //Auxiliary Register 1
+#define PCA_USE_P12P11P10P37() P_SW1 &= ~0x30 /* PCA/PWMлP12(ECI) P11(CCP0) P10(CCP1) P37(CCP2)(ϵĬ) */
+#define PCA_USE_P34P35P36P37() P_SW1 = (P_SW1 & ~0x30) | 0x10 /* PCA/PWMлP34(ECI) P35(CCP0) P36(CCP1) P37(CCP2) */
+#define PCA_USE_P24P25P26P27() P_SW1 = (P_SW1 & ~0x30) | 0x20 /* PCA/PWMлP24(ECI) P25(CCP0) P26(CCP1) P27(CCP2) */
+
+
+/* 7 6 5 4 3 2 1 0 Reset Value
+//sfr CCAPM0 = 0xDA; PWM Ĵ - ECOM0 CCAPP0 CCAPN0 MAT0 TOG0 PWM0 ECCF0 x000,0000 //PCA ģ0
+//sfr CCAPM1 = 0xDB; PWM Ĵ - ECOM1 CCAPP1 CCAPN1 MAT1 TOG1 PWM1 ECCF1 x000,0000 //PCA ģ1
+//sfr CCAPM2 = 0xDC; PWM Ĵ - ECOM2 CCAPP2 CCAPN2 MAT2 TOG2 PWM2 ECCF2 x000,0000 //PCA ģ2
+//sfr CCAPM3 = 0xDD; PWM Ĵ - ECOM3 CCAPP3 CCAPN3 MAT3 TOG3 PWM3 ECCF3 x000,0000 //PCA ģ3
+;ECOMn = 1: ȽϹܡ
+;CAPPn = 1: شܡ
+;CAPNn = 1: ½شܡ
+;MATn = 1: ƥʱCCONеCCFnλ
+;TOGn = 1: ƥʱCEXnת(CEX0/PCA0/PWM0/P3.7,CEX1/PCA1/PWM1/P3.5)
+;PWMn = 1: CEXnΪPWM
+;ECCFn = 1: CCONеCCFnжϡ
+;ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
+; 0 0 0 0 0 0 0 00H δκιܡ
+; x 1 0 0 0 0 x 20H 16λCEXnشܡ
+; x 0 1 0 0 0 x 10H 16λCEXn½شܡ
+; x 1 1 0 0 0 x 30H 16λCEXn/PCAnأϡأܡ
+; 1 0 0 1 0 0 x 48H 16λʱ
+; 1 0 0 1 1 0 x 4CH 16λ
+; 1 0 0 0 0 1 0 42H 8λPWMж
+; 1 1 0 0 0 1 1 63H 8λPWMͱ߿ɲж
+; 1 0 1 0 0 1 1 53H 8λPWM߱Ϳɲж
+; 1 1 1 0 0 1 1 73H 8λPWMͱ߱;ɲж
+;*******************************************************************
+;*******************************************************************/
+
+#define PCA0_none() CCAPM0 = 0
+#define PCA0_PWM(nbit) CCAPM0 = 0x42,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6)
+#define PCA0_PWM_rise_int(nbit) CCAPM0 = 0x63,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6)
+#define PCA0_PWM_fall_int(nbit) CCAPM0 = 0x53,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6)
+#define PCA0_PWM_edge_int(nbit) CCAPM0 = 0x73,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6)
+#define PCA0_capture_rise() CCAPM0 = (0x20 + 1)
+#define PCA0_capture_fall() CCAPM0 = (0x10 + 1)
+#define PCA0_capture_edge() CCAPM0 = (0x30 + 1)
+#define PCA0_16bit_Timer() CCAPM0 = (0x48 + 1)
+#define PCA0_High_PulseEnable() CCAPM0 |= 0x04
+
+#define PCA1_none() CCAPM1 = 0
+#define PCA1_PWM(nbit) CCAPM1 = 0x42,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6)
+#define PCA1_PWM_rise_int(nbit) CCAPM1 = 0x63,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6)
+#define PCA1_PWM_fall_int(nbit) CCAPM1 = 0x53,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6)
+#define PCA1_PWM_edge_int(nbit) CCAPM1 = 0x73,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6)
+#define PCA1_capture_rise() CCAPM1 = (0x20 + 1)
+#define PCA1_capture_fall() CCAPM1 = (0x10 + 1)
+#define PCA1_capture_edge() CCAPM1 = (0x30 + 1)
+#define PCA1_16bit_Timer() CCAPM1 = (0x48 + 1)
+#define PCA1_High_PulseEnable() CCAPM1 |= 0x04
+
+#define PCA2_none() CCAPM2 = 0
+#define PCA2_PWM(nbit) CCAPM2 = 0x42,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6)
+#define PCA2_PWM_rise_int(nbit) CCAPM2 = 0x63,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6)
+#define PCA2_PWM_fall_int(nbit) CCAPM2 = 0x53,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6)
+#define PCA2_PWM_edge_int(nbit) CCAPM2 = 0x73,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6)
+#define PCA2_capture_rise() CCAPM2 = (0x20 + 1)
+#define PCA2_capture_fall() CCAPM2 = (0x10 + 1)
+#define PCA2_capture_edge() CCAPM2 = (0x30 + 1)
+#define PCA2_16bit_Timer() CCAPM2 = (0x48 + 1)
+#define PCA2_High_PulseEnable() CCAPM2 |= 0x04
+
+//#define PCA3_none() CCAPM3 = 0
+//#define PCA3_PWM(nbit) CCAPM3 = 0x42,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6)
+//#define PCA3_PWM_rise_int(nbit) CCAPM3 = 0x63,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6)
+//#define PCA3_PWM_fall_int(nbit) CCAPM3 = 0x53,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6)
+//#define PCA3_PWM_edge_int(nbit) CCAPM3 = 0x73,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6)
+//#define PCA3_capture_rise() CCAPM3 = (0x20 + 1)
+//#define PCA3_capture_fall() CCAPM3 = (0x10 + 1)
+//#define PCA3_capture_edge() CCAPM3 = (0x30 + 1)
+//#define PCA3_16bit_Timer() CCAPM3 = (0x48 + 1)
+//#define PCA3_High_PulseEnable() CCAPM3 |= 0x04
+
+/**********************************************************/
+typedef unsigned char u8;
+typedef unsigned int u16;
+typedef unsigned long u32;
+
+/**********************************************************/
+#define NOP1() _nop_()
+#define NOP2() NOP1(),NOP1()
+#define NOP3() NOP2(),NOP1()
+#define NOP4() NOP3(),NOP1()
+#define NOP5() NOP4(),NOP1()
+#define NOP6() NOP5(),NOP1()
+#define NOP7() NOP6(),NOP1()
+#define NOP8() NOP7(),NOP1()
+#define NOP9() NOP8(),NOP1()
+#define NOP10() NOP9(),NOP1()
+#define NOP11() NOP10(),NOP1()
+#define NOP12() NOP11(),NOP1()
+#define NOP13() NOP12(),NOP1()
+#define NOP14() NOP13(),NOP1()
+#define NOP15() NOP14(),NOP1()
+#define NOP16() NOP15(),NOP1()
+#define NOP17() NOP16(),NOP1()
+#define NOP18() NOP17(),NOP1()
+#define NOP19() NOP18(),NOP1()
+#define NOP20() NOP19(),NOP1()
+#define NOP21() NOP20(),NOP1()
+#define NOP22() NOP21(),NOP1()
+#define NOP23() NOP22(),NOP1()
+#define NOP24() NOP23(),NOP1()
+#define NOP25() NOP24(),NOP1()
+#define NOP26() NOP25(),NOP1()
+#define NOP27() NOP26(),NOP1()
+#define NOP28() NOP27(),NOP1()
+#define NOP29() NOP28(),NOP1()
+#define NOP30() NOP29(),NOP1()
+#define NOP31() NOP30(),NOP1()
+#define NOP32() NOP31(),NOP1()
+#define NOP33() NOP32(),NOP1()
+#define NOP34() NOP33(),NOP1()
+#define NOP35() NOP34(),NOP1()
+#define NOP36() NOP35(),NOP1()
+#define NOP37() NOP36(),NOP1()
+#define NOP38() NOP37(),NOP1()
+#define NOP39() NOP38(),NOP1()
+#define NOP40() NOP39(),NOP1()
+#define NOP(N) NOP##N()
+
+
+/**********************************************/
+#define Pin0 0x01 //IO Px.0
+#define Pin1 0x02 //IO Px.1
+#define Pin2 0x04 //IO Px.2
+#define Pin3 0x08 //IO Px.3
+#define Pin4 0x10 //IO Px.4
+#define Pin5 0x20 //IO Px.5
+#define Pin6 0x40 //IO Px.6
+#define Pin7 0x80 //IO Px.7
+#define PinAll 0xFF //IO
+
+#define P0n_standard(bitn) P0M1 &= ~(bitn), P0M0 &= ~(bitn) /* 00 */
+#define P0n_push_pull(bitn) P0M1 &= ~(bitn), P0M0 |= (bitn) /* 01 */
+#define P0n_pure_input(bitn) P0M1 |= (bitn), P0M0 &= ~(bitn) /* 10 */
+#define P0n_open_drain(bitn) P0M1 |= (bitn), P0M0 |= (bitn) /* 11 */
+
+#define P1n_standard(bitn) P1M1 &= ~(bitn), P1M0 &= ~(bitn)
+#define P1n_push_pull(bitn) P1M1 &= ~(bitn), P1M0 |= (bitn)
+#define P1n_pure_input(bitn) P1M1 |= (bitn), P1M0 &= ~(bitn)
+#define P1n_open_drain(bitn) P1M1 |= (bitn), P1M0 |= (bitn)
+
+#define P2n_standard(bitn) P2M1 &= ~(bitn), P2M0 &= ~(bitn)
+#define P2n_push_pull(bitn) P2M1 &= ~(bitn), P2M0 |= (bitn)
+#define P2n_pure_input(bitn) P2M1 |= (bitn), P2M0 &= ~(bitn)
+#define P2n_open_drain(bitn) P2M1 |= (bitn), P2M0 |= (bitn)
+
+#define P3n_standard(bitn) P3M1 &= ~(bitn), P3M0 &= ~(bitn)
+#define P3n_push_pull(bitn) P3M1 &= ~(bitn), P3M0 |= (bitn)
+#define P3n_pure_input(bitn) P3M1 |= (bitn), P3M0 &= ~(bitn)
+#define P3n_open_drain(bitn) P3M1 |= (bitn), P3M0 |= (bitn)
+
+#define P4n_standard(bitn) P4M1 &= ~(bitn), P4M0 &= ~(bitn)
+#define P4n_push_pull(bitn) P4M1 &= ~(bitn), P4M0 |= (bitn)
+#define P4n_pure_input(bitn) P4M1 |= (bitn), P4M0 &= ~(bitn)
+#define P4n_open_drain(bitn) P4M1 |= (bitn), P4M0 |= (bitn)
+
+#define P5n_standard(bitn) P5M1 &= ~(bitn), P5M0 &= ~(bitn)
+#define P5n_push_pull(bitn) P5M1 &= ~(bitn), P5M0 |= (bitn)
+#define P5n_pure_input(bitn) P5M1 |= (bitn), P5M0 &= ~(bitn)
+#define P5n_open_drain(bitn) P5M1 |= (bitn), P5M0 |= (bitn)
+
+#define P6n_standard(bitn) P6M1 &= ~(bitn), P6M0 &= ~(bitn)
+#define P6n_push_pull(bitn) P6M1 &= ~(bitn), P6M0 |= (bitn)
+#define P6n_pure_input(bitn) P6M1 |= (bitn), P6M0 &= ~(bitn)
+#define P6n_open_drain(bitn) P6M1 |= (bitn), P6M0 |= (bitn)
+
+#define P7n_standard(bitn) P7M1 &= ~(bitn), P7M0 &= ~(bitn)
+#define P7n_push_pull(bitn) P7M1 &= ~(bitn), P7M0 |= (bitn)
+#define P7n_pure_input(bitn) P7M1 |= (bitn), P7M0 &= ~(bitn)
+#define P7n_open_drain(bitn) P7M1 |= (bitn), P7M0 |= (bitn)
+
+
+/****************************************************************/
+
+
+//sfr INT_CLKO = 0x8F; //ӵ SFR WAKE_CLKO (ַ0x8F)
+/*
+ 7 6 5 4 3 2 1 0 Reset Value
+ - EX4 EX3 EX2 - T2CLKO T1CLKO T0CLKO 0000,0000B
+b6 - EX4 : жINT4
+b5 - EX3 : жINT3
+b4 - EX2 : жINT2
+b2 - T1CLKO : T2 P3.0Fck1 = 1/2 T1
+b1 - T1CLKO : T1 P3.4Fck1 = 1/2 T1
+b0 - T0CLKO : T0 P3.5Fck0 = 1/2 T0
+*/
+
+#define LVD_InterruptEnable() ELVD = 1
+#define LVD_InterruptDisable() ELVD = 0
+
+
+//sfr WKTCL = 0xAA; //Ѷʱֽ
+//sfr WKTCH = 0xAB; //Ѷʱֽ
+// B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
+// WKTEN S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 n * 560us
+#define WakeTimerDisable() WKTCH &= 0x7f /* WKTEN = 0 ֹ˯Ѷʱ */
+#define WakeTimerSet(scale) WKTCL = (scale) % 256,WKTCH = (scale) / 256 | 0x80 /* WKTEN = 1 ˯Ѷʱ */
+
+
+
+//sfr BUS_SPEED = 0xA1; //Stretch register - - - - - - EXRTS1 EXRTSS0 xxxx,xx10
+#define BUS_SPEED_1T() BUS_SPEED = BUS_SPEED & ~3
+#define BUS_SPEED_2T() BUS_SPEED = (BUS_SPEED & ~3) | 1
+#define BUS_SPEED_4T() BUS_SPEED = (BUS_SPEED & ~3) | 2
+#define BUS_SPEED_8T() BUS_SPEED = (BUS_SPEED & ~3) | 3
+
+#define BUS_RD_WR_P44_P43() BUS_SPEED = BUS_SPEED & 0x3f
+#define BUS_RD_WR_P37_P36() BUS_SPEED = (BUS_SPEED & 0x3f) | 0x40
+#define BUS_RD_WR_P42_P40() BUS_SPEED = (BUS_SPEED & 0x3f) | 0x80
+
+
+/* interrupt vector */
+#define INT0_VECTOR 0
+#define TIMER0_VECTOR 1
+#define INT1_VECTOR 2
+#define TIMER1_VECTOR 3
+#define UART1_VECTOR 4
+#define ADC_VECTOR 5
+#define LVD_VECTOR 6
+#define PCA_VECTOR 7
+#define UART2_VECTOR 8
+#define SPI_VECTOR 9
+#define INT2_VECTOR 10
+#define INT3_VECTOR 11
+#define TIMER2_VECTOR 12
+#define INT4_VECTOR 16
+#define UART3_VECTOR 17
+#define UART4_VECTOR 18
+#define TIMER3_VECTOR 19
+#define TIMER4_VECTOR 20
+#define CMP_VECTOR 21
+#define PWM0_VECTOR 22
+#define PWMFD_VECTOR 23
+#define I2C_VECTOR 24
+#define USB_VECTOR 25
+#define PWMA_VECTOR 26
+#define PWMB_VECTOR 27
+#define PWM1_VECTOR 28
+#define PWM2_VECTOR 29
+#define PWM3_VECTOR 30
+#define PWM4_VECTOR 31
+#define PWM5_VECTOR 32
+
+
+#define TRUE 1
+#define FALSE 0
+
+//=============================================================
+
+//========================================
+
+#define Priority_0 0 //жȼΪ 0 ͼ
+#define Priority_1 1 //жȼΪ 1 ϵͼ
+#define Priority_2 2 //жȼΪ 2 ϸ
+#define Priority_3 3 //жȼΪ 3
+
+//========================================
+
+#define ENABLE 1
+#define DISABLE 0
+
+#endif
diff --git a/myinc/config.h b/myinc/config.h
new file mode 100644
index 0000000..1518746
--- /dev/null
+++ b/myinc/config.h
@@ -0,0 +1,33 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* ���Ҫ�ڳ�����ʹ�ô˴���,���ڳ�����ע��ʹ����STC�����ϼ����� */
+/*---------------------------------------------------------------------*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*********************************************************/
+
+//#define MAIN_Fosc 22118400L //������ʱ��
+//#define MAIN_Fosc 12000000L //������ʱ��
+#define MAIN_Fosc 11059200L //������ʱ��
+//#define MAIN_Fosc 5529600L //������ʱ��
+// #define MAIN_Fosc 24000000L //������ʱ��
+
+
+#define STC8Hxx //STC8Hϵ��
+//#define STC8Gxx //STC8Gϵ��
+
+/*********************************************************/
+
+#include "STC8xxxx.H"
+
+
+#endif
diff --git a/myinc/timer.h b/myinc/timer.h
new file mode 100644
index 0000000..d7909b3
--- /dev/null
+++ b/myinc/timer.h
@@ -0,0 +1,47 @@
+/*---------------------------------------------------------------------*/
+/* --- STC MCU Limited ------------------------------------------------*/
+/* --- STC 1T Series MCU Demo Programme -------------------------------*/
+/* --- Mobile: (86)13922805190 ----------------------------------------*/
+/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/
+/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/
+/* --- Web: www.STCMCU.com --------------------------------------------*/
+/* --- Web: www.STCMCUDATA.com ---------------------------------------*/
+/* --- QQ: 800003751 -------------------------------------------------*/
+/* ���Ҫ�ڳ�����ʹ�ô˴���,���ڳ�����ע��ʹ����STC�����ϼ����� */
+/*---------------------------------------------------------------------*/
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include "config.h"
+
+#define Timer0 0
+#define Timer1 1
+#define Timer2 2
+#define Timer3 3
+#define Timer4 4
+
+#define TIM_16BitAutoReload 0
+#define TIM_16Bit 1
+#define TIM_8BitAutoReload 2
+#define TIM_16BitAutoReloadNoMask 3
+
+#define TIM_CLOCK_1T 0
+#define TIM_CLOCK_12T 1
+#define TIM_CLOCK_Ext 2
+
+typedef struct
+{
+ u8 TIM_Mode; // ����ģʽ, TIM_16BitAutoReload,TIM_16Bit,TIM_8BitAutoReload,TIM_16BitAutoReloadNoMask
+ u8 TIM_Priority; // ���ȼ����� Priority_0,Priority_1,Priority_2,Priority_3
+ u8 TIM_Interrupt; // ����� ENABLE,DISABLE
+ u8 TIM_ClkSource; // ʱ��Դ TIM_CLOCK_1T,TIM_CLOCK_12T,TIM_CLOCK_Ext
+ u8 TIM_ClkOut; // �ɱ��ʱ�����, ENABLE,DISABLE
+ u16 TIM_Value; // װ�س�ֵ
+ u8 TIM_Run; // �Ƿ����� ENABLE,DISABLE
+} TIM_InitTypeDef;
+
+u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx);
+extern u8 KILL_time;
+void Timer_config(void);
+#endif