From 9a13d65e168efc188c0817b937d93ef0b05eef46 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=BE=90=E9=9D=92=E5=AE=87?= <10510612+xu-qingyuxx@user.noreply.gitee.com> Date: Mon, 10 Apr 2023 15:48:01 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=9E=E7=8E=B0kill=E6=8C=89=E9=94=AE?= =?UTF-8?q?=E5=A4=96=E9=83=A8=E4=B8=AD=E6=96=AD=20=E5=AF=B9p10-p12?= =?UTF-8?q?=E7=9A=84=E5=BC=80=E5=85=B3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .vscode/c_cpp_properties.json | 39 + .vscode/keil-assistant.log | 8 + .vscode/settings.json | 9 + .vscode/uv4.log | 10 + .vscode/uv4.log.lock | 1 + Listings/Exti.lst | 174 ++ Listings/GPIO.lst | 169 ++ Listings/STARTUP.lst | 253 +++ Listings/kill_control.m51 | 707 +++++++ Listings/main.lst | 52 + Listings/timer.lst | 210 +++ Objects/Exti.__i | 1 + Objects/Exti.obj | Bin 0 -> 109866 bytes Objects/GPIO.__i | 1 + Objects/GPIO.obj | Bin 0 -> 110035 bytes Objects/STARTUP.obj | Bin 0 -> 819 bytes Objects/kill_control | Bin 0 -> 435048 bytes Objects/kill_control.LIB | Bin 0 -> 11277 bytes Objects/kill_control.__b | 7 + Objects/kill_control.build_log.htm | 37 + Objects/kill_control.hex | 163 ++ Objects/kill_control.lnp | 7 + Objects/main.__i | 1 + Objects/main.obj | Bin 0 -> 105246 bytes Objects/timer.__i | 1 + Objects/timer.obj | Bin 0 -> 111985 bytes STARTUP.A51 | 198 ++ kill_control.uvgui.User | 1914 +++++++++++++++++++ kill_control.uvopt | 241 +++ kill_control.uvproj | 415 +++++ mycode/Exti.c | 143 ++ mycode/GPIO.c | 137 ++ mycode/main.c | 28 + mycode/timer.c | 176 ++ myinc/Exti.h | 38 + myinc/GPIO.h | 53 + myinc/STC8xxxx.H | 2747 ++++++++++++++++++++++++++++ myinc/config.h | 33 + myinc/timer.h | 47 + 39 files changed, 8020 insertions(+) create mode 100644 .vscode/c_cpp_properties.json create mode 100644 .vscode/keil-assistant.log create mode 100644 .vscode/settings.json create mode 100644 .vscode/uv4.log create mode 100644 .vscode/uv4.log.lock create mode 100644 Listings/Exti.lst create mode 100644 Listings/GPIO.lst create mode 100644 Listings/STARTUP.lst create mode 100644 Listings/kill_control.m51 create mode 100644 Listings/main.lst create mode 100644 Listings/timer.lst create mode 100644 Objects/Exti.__i create mode 100644 Objects/Exti.obj create mode 100644 Objects/GPIO.__i create mode 100644 Objects/GPIO.obj create mode 100644 Objects/STARTUP.obj create mode 100644 Objects/kill_control create mode 100644 Objects/kill_control.LIB create mode 100644 Objects/kill_control.__b create mode 100644 Objects/kill_control.build_log.htm create mode 100644 Objects/kill_control.hex create mode 100644 Objects/kill_control.lnp create mode 100644 Objects/main.__i create mode 100644 Objects/main.obj create mode 100644 Objects/timer.__i create mode 100644 Objects/timer.obj create mode 100644 STARTUP.A51 create mode 100644 kill_control.uvgui.User create mode 100644 kill_control.uvopt create mode 100644 kill_control.uvproj create mode 100644 mycode/Exti.c create mode 100644 mycode/GPIO.c create mode 100644 mycode/main.c create mode 100644 mycode/timer.c create mode 100644 myinc/Exti.h create mode 100644 myinc/GPIO.h create mode 100644 myinc/STC8xxxx.H create mode 100644 myinc/config.h create mode 100644 myinc/timer.h diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..b0a6341 --- /dev/null +++ b/.vscode/c_cpp_properties.json @@ -0,0 +1,39 @@ +{ + "configurations": [ + { + "name": "Target 1", + "includePath": [ + "d:\\Users\\User\\Documents\\peek250kill control\\myinc", + "D:\\Keil_v5\\C51\\INC", + "d:\\Users\\User\\Documents\\peek250kill control", + "d:\\Users\\User\\Documents\\peek250kill control\\mycode" + ], + "defines": [ + "__C51__", + "__VSCODE_C51__", + "reentrant=", + "compact=", + "small=", + "large=", + "data=", + "idata=", + "pdata=", + "bdata=", + "xdata=", + "code=", + "bit=char", + "sbit=char", + "sfr=char", + "sfr16=int", + "sfr32=int", + "interrupt=", + "using=", + "_at_=", + "_priority_=", + "_task_=" + ], + "intelliSenseMode": "${default}" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/.vscode/keil-assistant.log b/.vscode/keil-assistant.log new file mode 100644 index 0000000..be2a400 --- /dev/null +++ b/.vscode/keil-assistant.log @@ -0,0 +1,8 @@ +[info] Log at : 2023/4/10|15:03:01|GMT+0800 + +[info] Log at : 2023/4/10|15:03:11|GMT+0800 + +[info] Log at : 2023/4/10|15:46:14|GMT+0800 + +[info] Log at : 2023/4/10|15:46:58|GMT+0800 + diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..26f6d05 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,9 @@ +{ + "C_Cpp.errorSquiggles": "disabled", + "files.associations": { + "timer.h": "c", + "exti.h": "c", + "gpio.h": "c", + "config.h": "c" + } +} \ No newline at end of file diff --git a/.vscode/uv4.log b/.vscode/uv4.log new file mode 100644 index 0000000..7c98c7b --- /dev/null +++ b/.vscode/uv4.log @@ -0,0 +1,10 @@ +Build target 'Target 1' +compiling Exti.c... +compiling GPIO.c... +compiling main.c... +compiling timer.c... +linking... +Program Size: data=18.0 xdata=0 code=2183 +creating hex file from ".\Objects\kill_control"... +".\Objects\kill_control" - 0 Error(s), 0 Warning(s). +Build Time Elapsed: 00:00:00 diff --git a/.vscode/uv4.log.lock b/.vscode/uv4.log.lock new file mode 100644 index 0000000..85095db --- /dev/null +++ b/.vscode/uv4.log.lock @@ -0,0 +1 @@ +2023/4/10 15:47:04 \ No newline at end of file diff --git a/Listings/Exti.lst b/Listings/Exti.lst new file mode 100644 index 0000000..d21a1f4 --- /dev/null +++ b/Listings/Exti.lst @@ -0,0 +1,174 @@ +C51 COMPILER V9.60.0.0 EXTI 04/10/2023 15:47:03 PAGE 1 + + +C51 COMPILER V9.60.0.0, COMPILATION OF MODULE EXTI +OBJECT MODULE PLACED IN .\Objects\Exti.obj +COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\Exti.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEN + -D PRINT(.\Listings\Exti.lst) TABS(2) OBJECT(.\Objects\Exti.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 /************* ¹¦ÄÜ˵Ã÷ ************** + 14 + 15 ±¾ÎļþΪSTC8ϵÁеÄÍâÖжϳõʼ»¯ºÍÖжϳÌÐò,Óû§¿ÉÒÔÔÚÕâ¸öÎļþÖÐÐÞ¸Ä×Ô¼ºÐèÒªµÄÖжϳÌÐò. + 16 + 17 ******************************************/ + 18 + 19 #include "Exti.h" + 20 + 21 /************* Íⲿº¯ÊýºÍ±äÁ¿ÉùÃ÷ *****************/ + 22 + 23 /********************* INT0ÖжϺ¯Êý *************************/ + 24 void Ext_INT0(void) interrupt INT0_VECTOR // ½øÖжÏʱÒѾ­Çå³ý±êÖ¾ + 25 { + 26 1 if (kill_gpio) + 27 1 { + 28 2 if (KILL_time == 0) + 29 2 { + 30 3 power1_gpio = !power1_gpio; + 31 3 power2_gpio = !power2_gpio; + 32 3 power3_gpio = !power3_gpio; + 33 3 } + 34 2 } + 35 1 else + 36 1 { + 37 2 KILL_time = 50; + 38 2 } + 39 1 } + 40 + 41 /********************* INT1ÖжϺ¯Êý *************************/ + 42 void Ext_INT1(void) interrupt INT1_VECTOR // ½øÖжÏʱÒѾ­Çå³ý±êÖ¾ + 43 { + 44 1 } + 45 + 46 /********************* INT2ÖжϺ¯Êý *************************/ + 47 void Ext_INT2(void) interrupt INT2_VECTOR // + 48 { + 49 1 } + 50 + 51 /********************* INT3ÖжϺ¯Êý *************************/ + 52 void Ext_INT3(void) interrupt INT3_VECTOR + 53 { + 54 1 } + C51 COMPILER V9.60.0.0 EXTI 04/10/2023 15:47:03 PAGE 2 + + 55 + 56 /********************* INT4ÖжϺ¯Êý *************************/ + 57 void Ext_INT4(void) interrupt INT4_VECTOR + 58 { + 59 1 } + 60 + 61 //======================================================================== + 62 // º¯Êý: u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx) + 63 // ÃèÊö: ÍⲿÖжϳõʼ»¯³ÌÐò. + 64 // ²ÎÊý: INTx: ½á¹¹²ÎÊý,Çë²Î¿¼Exti.hÀïµÄ¶¨Òå. + 65 // ·µ»Ø: ³É¹¦·µ»Ø0, ¿Õ²Ù×÷·µ»Ø1,´íÎó·µ»Ø2. + 66 // °æ±¾: V1.0, 2012-10-22 + 67 //======================================================================== + 68 u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx) + 69 { + 70 1 if (EXT > EXT_INT4) + 71 1 return 1; // ¿Õ²Ù×÷ + 72 1 + 73 1 if (EXT == EXT_INT0) // ÍâÖжÏ0 + 74 1 { + 75 2 IE0 = 0; // ÍâÖжÏ0±ê־λ + 76 2 if (INTx->EXTI_Interrupt == ENABLE) + 77 2 EX0 = 1; // ÔÊÐíÖÐ¶Ï + 78 2 else + 79 2 EX0 = 0; // ½ûÖ¹ÖÐ¶Ï + 80 2 if (INTx->EXTI_Priority > Priority_3) + 81 2 return 2; // ´íÎó + 82 2 INT0_Priority(INTx->EXTI_Priority); // Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Pri + -ority_3 + 83 2 if (INTx->EXTI_Mode == EXT_MODE_Fall) + 84 2 IT0 = 1; // ϽµÑØÖÐ¶Ï + 85 2 else + 86 2 IT0 = 0; // ÉÏÉý,ϽµÑØÖÐ¶Ï + 87 2 return 0; // ³É¹¦ + 88 2 } + 89 1 + 90 1 if (EXT == EXT_INT1) // ÍâÖжÏ1 + 91 1 { + 92 2 IE1 = 0; // ÍâÖжÏ1±ê־λ + 93 2 if (INTx->EXTI_Interrupt == ENABLE) + 94 2 EX1 = 1; // ÔÊÐíÖÐ¶Ï + 95 2 else + 96 2 EX1 = 0; // ½ûÖ¹ÖÐ¶Ï + 97 2 if (INTx->EXTI_Priority > Priority_3) + 98 2 return 2; // ´íÎó + 99 2 INT1_Priority(INTx->EXTI_Priority); // Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Pri + -ority_3 + 100 2 if (INTx->EXTI_Mode == EXT_MODE_Fall) + 101 2 IT1 = 1; // ϽµÑØÖÐ¶Ï + 102 2 else + 103 2 IT1 = 0; // ÉÏÉý,ϽµÑØÖÐ¶Ï + 104 2 return 0; // ³É¹¦ + 105 2 } + 106 1 + 107 1 if (EXT == EXT_INT2) // ÍâÖжÏ2, ¹Ì¶¨ÎªÏ½µÑصÍÓÅÏȼ¶ÖÐ¶Ï + 108 1 { + 109 2 if (INTx->EXTI_Interrupt == ENABLE) + 110 2 INT_CLKO |= (1 << 4); // ÔÊÐíÖÐ¶Ï + 111 2 else + 112 2 INT_CLKO &= ~(1 << 4); // ½ûÖ¹ÖÐ¶Ï + 113 2 return 0; // ³É¹¦ + 114 2 } + C51 COMPILER V9.60.0.0 EXTI 04/10/2023 15:47:03 PAGE 3 + + 115 1 + 116 1 if (EXT == EXT_INT3) // ÍâÖжÏ3, ¹Ì¶¨ÎªÏ½µÑصÍÓÅÏȼ¶ÖÐ¶Ï + 117 1 { + 118 2 if (INTx->EXTI_Interrupt == ENABLE) + 119 2 INT_CLKO |= (1 << 5); // ÔÊÐíÖÐ¶Ï + 120 2 else + 121 2 INT_CLKO &= ~(1 << 5); // ½ûÖ¹ÖÐ¶Ï + 122 2 return 0; // ³É¹¦ + 123 2 } + 124 1 + 125 1 if (EXT == EXT_INT4) // ÍâÖжÏ4, ¹Ì¶¨ÎªÏ½µÑصÍÓÅÏȼ¶ÖÐ¶Ï + 126 1 { + 127 2 if (INTx->EXTI_Interrupt == ENABLE) + 128 2 INT_CLKO |= (1 << 6); // ÔÊÐíÖÐ¶Ï + 129 2 else + 130 2 INT_CLKO &= ~(1 << 6); // ½ûÖ¹ÖÐ¶Ï + 131 2 return 0; // ³É¹¦ + 132 2 } + 133 1 return 2; // ʧ°Ü + 134 1 } + 135 void Exti_config(void) + 136 { + 137 1 EXTI_InitTypeDef Exti_InitStructure; // ½á¹¹¶¨Òå + 138 1 + 139 1 Exti_InitStructure.EXTI_Interrupt = ENABLE; // ÖжÏʹÄÜ, ENABLE»òDISABLE + 140 1 Exti_InitStructure.EXTI_Mode = EXT_MODE_RiseFall; // ÖжÏģʽ, EXT_MODE_RiseFall,EXT_MODE_Fall + 141 1 Exti_InitStructure.EXTI_Priority = Priority_0; // Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Prio + -rity_2,Priority_3 + 142 1 Ext_Inilize(EXT_INT0, &Exti_InitStructure); // ³õʼ»¯ + 143 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 340 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- 3 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/GPIO.lst b/Listings/GPIO.lst new file mode 100644 index 0000000..37fa8d2 --- /dev/null +++ b/Listings/GPIO.lst @@ -0,0 +1,169 @@ +C51 COMPILER V9.60.0.0 GPIO 04/10/2023 15:47:03 PAGE 1 + + +C51 COMPILER V9.60.0.0, COMPILATION OF MODULE GPIO +OBJECT MODULE PLACED IN .\Objects\GPIO.obj +COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\GPIO.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEN + -D PRINT(.\Listings\GPIO.lst) TABS(2) OBJECT(.\Objects\GPIO.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 /*************** ¹¦ÄÜ˵Ã÷ **************** + 14 + 15 ±¾ÎļþΪSTC8ϵÁеĶ˿ڳõʼ»¯³ÌÐò,Óû§¼¸ºõ¿ÉÒÔ²»ÐÞ¸ÄÕâ¸ö³ÌÐò. + 16 + 17 ******************************************/ + 18 + 19 #include "GPIO.h" + 20 + 21 //======================================================================== + 22 // º¯Êý: u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) + 23 // ÃèÊö: ³õʼ»¯IO¿Ú. + 24 // ²ÎÊý: GPIOx: ½á¹¹²ÎÊý,Çë²Î¿¼timer.hÀïµÄ¶¨Òå. + 25 // ·µ»Ø: ³É¹¦·µ»Ø0, ¿Õ²Ù×÷·µ»Ø1,´íÎó·µ»Ø2. + 26 // °æ±¾: V1.0, 2012-10-22 + 27 //======================================================================== + 28 u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) + 29 { + 30 1 if (GPIO > GPIO_P7) + 31 1 return 1; // ¿Õ²Ù×÷ + 32 1 if (GPIOx->Mode > GPIO_OUT_PP) + 33 1 return 2; // ´íÎó + 34 1 if (GPIO == GPIO_P0) + 35 1 { + 36 2 if (GPIOx->Mode == GPIO_PullUp) + 37 2 P0M1 &= ~GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 38 2 if (GPIOx->Mode == GPIO_HighZ) + 39 2 P0M1 |= GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 40 2 if (GPIOx->Mode == GPIO_OUT_OD) + 41 2 P0M1 |= GPIOx->Pin, P0M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 42 2 if (GPIOx->Mode == GPIO_OUT_PP) + 43 2 P0M1 &= ~GPIOx->Pin, P0M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 44 2 } + 45 1 if (GPIO == GPIO_P1) + 46 1 { + 47 2 if (GPIOx->Mode == GPIO_PullUp) + 48 2 P1M1 &= ~GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 49 2 if (GPIOx->Mode == GPIO_HighZ) + 50 2 P1M1 |= GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 51 2 if (GPIOx->Mode == GPIO_OUT_OD) + 52 2 P1M1 |= GPIOx->Pin, P1M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 53 2 if (GPIOx->Mode == GPIO_OUT_PP) + 54 2 P1M1 &= ~GPIOx->Pin, P1M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + C51 COMPILER V9.60.0.0 GPIO 04/10/2023 15:47:03 PAGE 2 + + 55 2 } + 56 1 if (GPIO == GPIO_P2) + 57 1 { + 58 2 if (GPIOx->Mode == GPIO_PullUp) + 59 2 P2M1 &= ~GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 60 2 if (GPIOx->Mode == GPIO_HighZ) + 61 2 P2M1 |= GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 62 2 if (GPIOx->Mode == GPIO_OUT_OD) + 63 2 P2M1 |= GPIOx->Pin, P2M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 64 2 if (GPIOx->Mode == GPIO_OUT_PP) + 65 2 P2M1 &= ~GPIOx->Pin, P2M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 66 2 } + 67 1 if (GPIO == GPIO_P3) + 68 1 { + 69 2 if (GPIOx->Mode == GPIO_PullUp) + 70 2 P3M1 &= ~GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 71 2 if (GPIOx->Mode == GPIO_HighZ) + 72 2 P3M1 |= GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 73 2 if (GPIOx->Mode == GPIO_OUT_OD) + 74 2 P3M1 |= GPIOx->Pin, P3M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 75 2 if (GPIOx->Mode == GPIO_OUT_PP) + 76 2 P3M1 &= ~GPIOx->Pin, P3M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 77 2 } + 78 1 if (GPIO == GPIO_P4) + 79 1 { + 80 2 if (GPIOx->Mode == GPIO_PullUp) + 81 2 P4M1 &= ~GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 82 2 if (GPIOx->Mode == GPIO_HighZ) + 83 2 P4M1 |= GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 84 2 if (GPIOx->Mode == GPIO_OUT_OD) + 85 2 P4M1 |= GPIOx->Pin, P4M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 86 2 if (GPIOx->Mode == GPIO_OUT_PP) + 87 2 P4M1 &= ~GPIOx->Pin, P4M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 88 2 } + 89 1 if (GPIO == GPIO_P5) + 90 1 { + 91 2 if (GPIOx->Mode == GPIO_PullUp) + 92 2 P5M1 &= ~GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 93 2 if (GPIOx->Mode == GPIO_HighZ) + 94 2 P5M1 |= GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 95 2 if (GPIOx->Mode == GPIO_OUT_OD) + 96 2 P5M1 |= GPIOx->Pin, P5M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 97 2 if (GPIOx->Mode == GPIO_OUT_PP) + 98 2 P5M1 &= ~GPIOx->Pin, P5M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 99 2 } + 100 1 if (GPIO == GPIO_P6) + 101 1 { + 102 2 if (GPIOx->Mode == GPIO_PullUp) + 103 2 P6M1 &= ~GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 104 2 if (GPIOx->Mode == GPIO_HighZ) + 105 2 P6M1 |= GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + 106 2 if (GPIOx->Mode == GPIO_OUT_OD) + 107 2 P6M1 |= GPIOx->Pin, P6M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 108 2 if (GPIOx->Mode == GPIO_OUT_PP) + 109 2 P6M1 &= ~GPIOx->Pin, P6M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 110 2 } + 111 1 if (GPIO == GPIO_P7) + 112 1 { + 113 2 if (GPIOx->Mode == GPIO_PullUp) + 114 2 P7M1 &= ~GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + 115 2 if (GPIOx->Mode == GPIO_HighZ) + 116 2 P7M1 |= GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + C51 COMPILER V9.60.0.0 GPIO 04/10/2023 15:47:03 PAGE 3 + + 117 2 if (GPIOx->Mode == GPIO_OUT_OD) + 118 2 P7M1 |= GPIOx->Pin, P7M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + 119 2 if (GPIOx->Mode == GPIO_OUT_PP) + 120 2 P7M1 &= ~GPIOx->Pin, P7M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + 121 2 } + 122 1 return 0; // ³É¹¦ + 123 1 } + 124 void GPIO_config(void) + 125 { + 126 1 GPIO_InitTypeDef GPIO_InitStructure; // ½á¹¹¶¨Òå + 127 1 + 128 1 GPIO_InitStructure.Pin = GPIO_Pin_2; // Ö¸¶¨Òª³õʼ»¯µÄIO, GPIO_Pin_0 ~ GPIO_ + -Pin_7, »ò²Ù×÷ + 129 1 GPIO_InitStructure.Mode = GPIO_PullUp; // Ö¸¶¨IOµÄÊäÈë»òÊä³ö·½Ê½,GPIO_PullUp,G + -PIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + 130 1 GPIO_Inilize(GPIO_P3, &GPIO_InitStructure); // ³õʼ»¯ + 131 1 GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2; // Ö¸¶¨Òª³õʼ»¯µÄIO, GPIO_Pin_0 ~ GPIO_ + -Pin_7, »ò²Ù×÷ + 132 1 GPIO_InitStructure.Mode = GPIO_OUT_PP; // Ö¸¶¨IOµÄÊäÈë»òÊä³ö·½Ê½,GPIO_PullUp,G + -PIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + 133 1 GPIO_Inilize(GPIO_P1, &GPIO_InitStructure); // ³õʼ»¯ + 134 1 power1_gpio = 0; + 135 1 power2_gpio = 0; + 136 1 power3_gpio = 0; + 137 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 665 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- 2 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/STARTUP.lst b/Listings/STARTUP.lst new file mode 100644 index 0000000..d72e3cc --- /dev/null +++ b/Listings/STARTUP.lst @@ -0,0 +1,253 @@ +A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 1 + + +MACRO ASSEMBLER A51 V8.2.7.0 +OBJECT MODULE PLACED IN .\Objects\STARTUP.obj +ASSEMBLER INVOKED BY: d:\Keil_v5\C51\BIN\A51.EXE STARTUP.A51 SET(SMALL) DEBUG PRINT(.\Listings\STARTUP.lst) OBJECT(.\Obj + ects\STARTUP.obj) EP + +LOC OBJ LINE SOURCE + + 1 $nomod51 + 2 ;------------------------------------------------------------------------------ + 3 ; This file is part of the C51 Compiler package + 4 ; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. + 5 ; Version 8.01 + 6 ; + 7 ; *** <<< Use Configuration Wizard in Context Menu >>> *** + 8 ;------------------------------------------------------------------------------ + 9 ; STARTUP.A51: This code is executed after processor reset. + 10 ; + 11 ; To translate this file use A51 with the following invocation: + 12 ; + 13 ; A51 STARTUP.A51 + 14 ; + 15 ; To link the modified STARTUP.OBJ file to your application use the following + 16 ; Lx51 invocation: + 17 ; + 18 ; Lx51 your object file list, STARTUP.OBJ controls + 19 ; + 20 ;------------------------------------------------------------------------------ + 21 ; + 22 ; User-defined Power-On Initialization of Memory + 23 ; + 24 ; With the following EQU statements the initialization of memory + 25 ; at processor reset can be defined: + 26 ; + 27 ; IDATALEN: IDATA memory size <0x0-0x100> + 28 ; Note: The absolute start-address of IDATA memory is always 0 + 29 ; The IDATA space overlaps physically the DATA and BIT areas. + 0080 30 IDATALEN EQU 80H + 31 ; + 32 ; XDATASTART: XDATA memory start address <0x0-0xFFFF> + 33 ; The absolute start address of XDATA memory + 0000 34 XDATASTART EQU 0 + 35 ; + 36 ; XDATALEN: XDATA memory size <0x0-0xFFFF> + 37 ; The length of XDATA memory in bytes. + 0000 38 XDATALEN EQU 0 + 39 ; + 40 ; PDATASTART: PDATA memory start address <0x0-0xFFFF> + 41 ; The absolute start address of PDATA memory + 0000 42 PDATASTART EQU 0H + 43 ; + 44 ; PDATALEN: PDATA memory size <0x0-0xFF> + 45 ; The length of PDATA memory in bytes. + 0000 46 PDATALEN EQU 0H + 47 ; + 48 ; + 49 ;------------------------------------------------------------------------------ + 50 ; + 51 ; Reentrant Stack Initialization + 52 ; + 53 ; The following EQU statements define the stack pointer for reentrant + 54 ; functions and initialized it: + 55 ; + 56 ; Stack Space for reentrant functions in the SMALL model. + 57 ; IBPSTACK: Enable SMALL model reentrant stack + A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 2 + + 58 ; Stack space for reentrant functions in the SMALL model. + 0000 59 IBPSTACK EQU 0 ; set to 1 if small reentrant is used. + 60 ; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> + 61 ; Set the top of the stack to the highest location. + 0100 62 IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 + 63 ; + 64 ; + 65 ; Stack Space for reentrant functions in the LARGE model. + 66 ; XBPSTACK: Enable LARGE model reentrant stack + 67 ; Stack space for reentrant functions in the LARGE model. + 0000 68 XBPSTACK EQU 0 ; set to 1 if large reentrant is used. + 69 ; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> + 70 ; Set the top of the stack to the highest location. + 0000 71 XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 + 72 ; + 73 ; + 74 ; Stack Space for reentrant functions in the COMPACT model. + 75 ; PBPSTACK: Enable COMPACT model reentrant stack + 76 ; Stack space for reentrant functions in the COMPACT model. + 0000 77 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. + 78 ; + 79 ; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> + 80 ; Set the top of the stack to the highest location. + 0100 81 PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 + 82 ; + 83 ; + 84 ;------------------------------------------------------------------------------ + 85 ; + 86 ; Memory Page for Using the Compact Model with 64 KByte xdata RAM + 87 ; Compact Model Page Definition + 88 ; + 89 ; Define the XDATA page used for PDATA variables. + 90 ; PPAGE must conform with the PPAGE set in the linker invocation. + 91 ; + 92 ; Enable pdata memory page initalization + 0000 93 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. + 94 ; + 95 ; PPAGE number <0x0-0xFF> + 96 ; uppermost 256-byte address of the page used for PDATA variables. + 0000 97 PPAGE EQU 0 + 98 ; + 99 ; SFR address which supplies uppermost address byte <0x0-0xFF> + 100 ; most 8051 variants use P2 as uppermost address byte + 00A0 101 PPAGE_SFR DATA 0A0H + 102 ; + 103 ; + 104 ;------------------------------------------------------------------------------ + 105 + 106 ; Standard SFR Symbols + 00E0 107 ACC DATA 0E0H + 00F0 108 B DATA 0F0H + 0081 109 SP DATA 81H + 0082 110 DPL DATA 82H + 0083 111 DPH DATA 83H + 112 + 113 NAME ?C_STARTUP + 114 + 115 + 116 ?C_C51STARTUP SEGMENT CODE + 117 ?STACK SEGMENT IDATA + 118 +---- 119 RSEG ?STACK +0000 120 DS 1 + 121 + 122 EXTRN CODE (?C_START) + 123 PUBLIC ?C_STARTUP + A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 3 + + 124 +---- 125 CSEG AT 0 +0000 020000 F 126 ?C_STARTUP: LJMP STARTUP1 + 127 +---- 128 RSEG ?C_C51STARTUP + 129 +0000 130 STARTUP1: + 131 + 132 IF IDATALEN <> 0 +0000 787F 133 MOV R0,#IDATALEN - 1 +0002 E4 134 CLR A +0003 F6 135 IDATALOOP: MOV @R0,A +0004 D8FD 136 DJNZ R0,IDATALOOP + 137 ENDIF + 138 + 139 IF XDATALEN <> 0 + MOV DPTR,#XDATASTART + MOV R7,#LOW (XDATALEN) + IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE + MOV R6,#HIGH (XDATALEN) + ENDIF + CLR A + XDATALOOP: MOVX @DPTR,A + INC DPTR + DJNZ R7,XDATALOOP + DJNZ R6,XDATALOOP + ENDIF + 153 + 154 IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE + ENDIF + 157 + 158 IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A + PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP + ENDIF + 166 + 167 IF IBPSTACK <> 0 + EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP + ENDIF + 172 + 173 IF XBPSTACK <> 0 + EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP + ENDIF + 179 + 180 IF PBPSTACK <> 0 + EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP + ENDIF + 184 +0006 758100 F 185 MOV SP,#?STACK-1 + 186 + 187 ; This code is required if you use L51_BANK.A51 with Banking Mode 4 + 188 ; Code Banking + 189 ; Select Bank 0 for L51_BANK.A51 Mode 4 + A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 4 + + 190 + + + + + 195 ; +0009 020000 F 196 LJMP ?C_START + 197 + 198 END + A51 MACRO ASSEMBLER STARTUP 04/10/2023 14:45:02 PAGE 5 + +SYMBOL TABLE LISTING +------ ----- ------- + + +N A M E T Y P E V A L U E ATTRIBUTES + +?C_C51STARTUP. . . C SEG 000CH REL=UNIT +?C_START . . . . . C ADDR ----- EXT +?C_STARTUP . . . . C ADDR 0000H A +?STACK . . . . . . I SEG 0001H REL=UNIT +ACC. . . . . . . . D ADDR 00E0H A +B. . . . . . . . . D ADDR 00F0H A +DPH. . . . . . . . D ADDR 0083H A +DPL. . . . . . . . D ADDR 0082H A +IBPSTACK . . . . . N NUMB 0000H A +IBPSTACKTOP. . . . N NUMB 0100H A +IDATALEN . . . . . N NUMB 0080H A +IDATALOOP. . . . . C ADDR 0003H R SEG=?C_C51STARTUP +PBPSTACK . . . . . N NUMB 0000H A +PBPSTACKTOP. . . . N NUMB 0100H A +PDATALEN . . . . . N NUMB 0000H A +PDATASTART . . . . N NUMB 0000H A +PPAGE. . . . . . . N NUMB 0000H A +PPAGEENABLE. . . . N NUMB 0000H A +PPAGE_SFR. . . . . D ADDR 00A0H A +SP . . . . . . . . D ADDR 0081H A +STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP +XBPSTACK . . . . . N NUMB 0000H A +XBPSTACKTOP. . . . N NUMB 0000H A +XDATALEN . . . . . N NUMB 0000H A +XDATASTART . . . . N NUMB 0000H A + + +REGISTER BANK(S) USED: 0 + + +ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/kill_control.m51 b/Listings/kill_control.m51 new file mode 100644 index 0000000..22471f6 --- /dev/null +++ b/Listings/kill_control.m51 @@ -0,0 +1,707 @@ +BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 1 + + +BL51 BANKED LINKER/LOCATER V6.22.2.0, INVOKED BY: +D:\KEIL_V5\C51\BIN\BL51.EXE .\Objects\STARTUP.obj, .\Objects\Exti.obj, .\Objects\GPIO.obj, .\Objects\main.obj, .\Objects +>> \timer.obj TO .\Objects\kill_control PRINT (.\Listings\kill_control.m51) RAMSIZE (256) + + +MEMORY MODEL: SMALL + + +INPUT MODULES INCLUDED: + .\Objects\STARTUP.obj (?C_STARTUP) + .\Objects\Exti.obj (EXTI) + .\Objects\GPIO.obj (GPIO) + .\Objects\main.obj (MAIN) + .\Objects\timer.obj (TIMER) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C_INIT) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?CLDPTR) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?CLDOPTR) + D:\KEIL_V5\C51\LIB\C51S.LIB (?C?ILDOPTR) + + +LINK MAP OF MODULE: .\Objects\kill_control (?C_STARTUP) + + + TYPE BASE LENGTH RELOCATION SEGMENT NAME + ----------------------------------------------------- + + * * * * * * * D A T A M E M O R Y * * * * * * * + REG 0000H 0008H ABSOLUTE "REG BANK 0" + DATA 0008H 0008H UNIT _DATA_GROUP_ + DATA 0010H 0001H UNIT ?DT?TIMER + IDATA 0011H 0001H UNIT ?STACK + + * * * * * * * C O D E M E M O R Y * * * * * * * + CODE 0000H 0003H ABSOLUTE + CODE 0003H 0003H ABSOLUTE + CODE 0006H 0004H UNIT ?C_INITSEG + CODE 000AH 0001H UNIT ?PR?EXT_INT1?EXTI + CODE 000BH 0003H ABSOLUTE + CODE 000EH 0001H UNIT ?PR?EXT_INT2?EXTI + CODE 000FH 0001H UNIT ?PR?EXT_INT3?EXTI + CODE 0010H 0001H UNIT ?PR?EXT_INT4?EXTI + CODE 0011H 0001H UNIT ?PR?TIMER1_INT?TIMER + CODE 0012H 0001H UNIT ?PR?TIMER2_INT?TIMER + CODE 0013H 0003H ABSOLUTE + CODE 0016H 0001H UNIT ?PR?TIMER3_INT?TIMER + CODE 0017H 0001H UNIT ?PR?TIMER4_INT?TIMER + 0018H 0003H *** GAP *** + CODE 001BH 0003H ABSOLUTE + CODE 001EH 0022H UNIT ?PR?GPIO_CONFIG?GPIO + CODE 0040H 0011H UNIT ?PR?EXTI_CONFIG?EXTI + 0051H 0002H *** GAP *** + CODE 0053H 0003H ABSOLUTE + 0056H 0005H *** GAP *** + CODE 005BH 0003H ABSOLUTE + 005EH 0005H *** GAP *** + CODE 0063H 0003H ABSOLUTE + CODE 0066H 0017H UNIT ?PR?EXT_INT0?EXTI + 007DH 0006H *** GAP *** + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 2 + + + CODE 0083H 0003H ABSOLUTE + CODE 0086H 000DH UNIT ?PR?MAIN?MAIN + 0093H 0008H *** GAP *** + CODE 009BH 0003H ABSOLUTE + 009EH 0005H *** GAP *** + CODE 00A3H 0003H ABSOLUTE + CODE 00A6H 0331H UNIT ?PR?_TIMER_INILIZE?TIMER + CODE 03D7H 0277H UNIT ?PR?_GPIO_INILIZE?GPIO + CODE 064EH 0128H UNIT ?PR?_EXT_INILIZE?EXTI + CODE 0776H 008CH UNIT ?C_C51STARTUP + CODE 0802H 007EH UNIT ?C?LIB_CODE + CODE 0880H 001EH UNIT ?PR?TIMER_CONFIG?TIMER + CODE 089EH 000BH UNIT ?PR?TIMER0_INT?TIMER + + + +OVERLAY MAP OF MODULE: .\Objects\kill_control (?C_STARTUP) + + +SEGMENT DATA_GROUP + +--> CALLED SEGMENT START LENGTH +------------------------------------------------ +?C_C51STARTUP ----- ----- + +--> ?PR?MAIN?MAIN + +--> ?C_INITSEG + +?PR?MAIN?MAIN ----- ----- + +--> ?PR?GPIO_CONFIG?GPIO + +--> ?PR?EXTI_CONFIG?EXTI + +--> ?PR?TIMER_CONFIG?TIMER + +?PR?GPIO_CONFIG?GPIO 0008H 0002H + +--> ?PR?_GPIO_INILIZE?GPIO + +?PR?EXTI_CONFIG?EXTI 0008H 0003H + +--> ?PR?_EXT_INILIZE?EXTI + +?PR?TIMER_CONFIG?TIMER 0008H 0008H + +--> ?PR?_TIMER_INILIZE?TIMER + + + +SYMBOL TABLE OF MODULE: .\Objects\kill_control (?C_STARTUP) + + VALUE TYPE NAME + ---------------------------------- + + ------- MODULE ?C_STARTUP + C:0776H SEGMENT ?C_C51STARTUP + I:0011H SEGMENT ?STACK + C:0000H PUBLIC ?C_STARTUP + D:00E0H SYMBOL ACC + D:00F0H SYMBOL B + D:0083H SYMBOL DPH + D:0082H SYMBOL DPL + N:0000H SYMBOL IBPSTACK + N:0100H SYMBOL IBPSTACKTOP + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 3 + + + N:0080H SYMBOL IDATALEN + C:0779H SYMBOL IDATALOOP + N:0000H SYMBOL PBPSTACK + N:0100H SYMBOL PBPSTACKTOP + N:0000H SYMBOL PDATALEN + N:0000H SYMBOL PDATASTART + N:0000H SYMBOL PPAGE + N:0000H SYMBOL PPAGEENABLE + D:00A0H SYMBOL PPAGE_SFR + D:0081H SYMBOL SP + C:0776H SYMBOL STARTUP1 + N:0000H SYMBOL XBPSTACK + N:0000H SYMBOL XBPSTACKTOP + N:0000H SYMBOL XDATALEN + N:0000H SYMBOL XDATASTART + C:0000H LINE# 126 + C:0776H LINE# 133 + C:0778H LINE# 134 + C:0779H LINE# 135 + C:077AH LINE# 136 + C:077CH LINE# 185 + C:077FH LINE# 196 + ------- ENDMOD ?C_STARTUP + + ------- MODULE EXTI + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + C:0066H PUBLIC Ext_INT0 + C:000AH PUBLIC Ext_INT1 + C:000EH PUBLIC Ext_INT2 + B:0090H.0 PUBLIC P10 + C:000FH PUBLIC Ext_INT3 + B:0090H.1 PUBLIC P11 + C:0010H PUBLIC Ext_INT4 + B:0090H.2 PUBLIC P12 + D:0098H PUBLIC SCON + B:00B0H.2 PUBLIC P32 + D:0088H PUBLIC TCON + B:0088H.1 PUBLIC IE0 + B:0088H.3 PUBLIC IE1 + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + B:00A8H.0 PUBLIC EX0 + B:0088H.0 PUBLIC IT0 + B:00A8H.2 PUBLIC EX1 + B:0088H.2 PUBLIC IT1 + B:00B8H.0 PUBLIC PX0 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 4 + + + B:00B8H.2 PUBLIC PX1 + D:00B7H PUBLIC IPH + C:064EH PUBLIC _Ext_Inilize + C:0040H PUBLIC Exti_config + D:008FH PUBLIC INT_CLKO + D:00D0H PUBLIC PSW + ------- PROC EXT_INT0 + C:0066H LINE# 24 + C:0068H LINE# 26 + C:006BH LINE# 27 + C:006BH LINE# 28 + C:006FH LINE# 29 + C:006FH LINE# 30 + C:0071H LINE# 31 + C:0073H LINE# 32 + C:0075H LINE# 33 + C:0075H LINE# 34 + C:0077H LINE# 36 + C:0077H LINE# 37 + C:007AH LINE# 38 + C:007AH LINE# 39 + ------- ENDPROC EXT_INT0 + ------- PROC EXT_INT1 + C:000AH LINE# 42 + C:000AH LINE# 44 + ------- ENDPROC EXT_INT1 + ------- PROC EXT_INT2 + C:000EH LINE# 47 + C:000EH LINE# 49 + ------- ENDPROC EXT_INT2 + ------- PROC EXT_INT3 + C:000FH LINE# 52 + C:000FH LINE# 54 + ------- ENDPROC EXT_INT3 + ------- PROC EXT_INT4 + C:0010H LINE# 57 + C:0010H LINE# 59 + ------- ENDPROC EXT_INT4 + ------- PROC _EXT_INILIZE + D:0007H SYMBOL EXT + D:0001H SYMBOL INTx + C:064EH LINE# 68 + C:064EH LINE# 69 + C:064EH LINE# 70 + C:0658H LINE# 71 + C:065BH LINE# 73 + C:065EH LINE# 74 + C:065EH LINE# 75 + C:0660H LINE# 76 + C:066AH LINE# 77 + C:066EH LINE# 79 + C:0670H LINE# 80 + C:0680H LINE# 81 + C:0683H LINE# 82 + C:06AFH LINE# 83 + C:06B6H LINE# 84 + C:06BAH LINE# 86 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 5 + + + C:06BCH LINE# 87 + C:06BFH LINE# 88 + C:06BFH LINE# 90 + C:06C4H LINE# 91 + C:06C4H LINE# 92 + C:06C6H LINE# 93 + C:06D0H LINE# 94 + C:06D4H LINE# 96 + C:06D6H LINE# 97 + C:06E6H LINE# 98 + C:06E9H LINE# 99 + C:0715H LINE# 100 + C:071CH LINE# 101 + C:0720H LINE# 103 + C:0722H LINE# 104 + C:0725H LINE# 105 + C:0725H LINE# 107 + C:072AH LINE# 108 + C:072AH LINE# 109 + C:0734H LINE# 110 + C:0739H LINE# 112 + C:073CH LINE# 113 + C:073FH LINE# 114 + C:073FH LINE# 116 + C:0744H LINE# 117 + C:0744H LINE# 118 + C:074EH LINE# 119 + C:0753H LINE# 121 + C:0756H LINE# 122 + C:0759H LINE# 123 + C:0759H LINE# 125 + C:075EH LINE# 126 + C:075EH LINE# 127 + C:0768H LINE# 128 + C:076DH LINE# 130 + C:0770H LINE# 131 + C:0773H LINE# 132 + C:0773H LINE# 133 + C:0775H LINE# 134 + ------- ENDPROC _EXT_INILIZE + ------- PROC EXTI_CONFIG + ------- DO + D:0008H SYMBOL Exti_InitStructure + ------- ENDDO + C:0040H LINE# 135 + C:0040H LINE# 136 + C:0040H LINE# 139 + C:0043H LINE# 140 + C:0046H LINE# 141 + C:0048H LINE# 142 + ------- ENDPROC EXTI_CONFIG + ------- ENDMOD EXTI + + ------- MODULE GPIO + C:0000H SYMBOL _ICE_DUMMY_ + D:0093H PUBLIC P0M1 + D:0092H PUBLIC P1M0 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 6 + + + D:0096H PUBLIC P2M0 + D:0091H PUBLIC P1M1 + D:0080H PUBLIC P0 + D:00B2H PUBLIC P3M0 + D:0095H PUBLIC P2M1 + D:0090H PUBLIC P1 + D:00B4H PUBLIC P4M0 + D:00B1H PUBLIC P3M1 + D:00A0H PUBLIC P2 + D:00CAH PUBLIC P5M0 + D:00B3H PUBLIC P4M1 + D:00B0H PUBLIC P3 + D:00CCH PUBLIC P6M0 + D:00C9H PUBLIC P5M1 + D:00C0H PUBLIC P4 + D:00E2H PUBLIC P7M0 + D:00CBH PUBLIC P6M1 + D:00C8H PUBLIC P5 + D:00E8H PUBLIC P6 + D:00E1H PUBLIC P7M1 + D:00F8H PUBLIC P7 + C:001EH PUBLIC GPIO_config + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + B:0090H.0 PUBLIC P10 + B:0090H.1 PUBLIC P11 + B:0090H.2 PUBLIC P12 + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + C:03D7H PUBLIC _GPIO_Inilize + D:00D0H PUBLIC PSW + D:0094H PUBLIC P0M0 + ------- PROC _GPIO_INILIZE + D:0007H SYMBOL GPIO + D:0001H SYMBOL GPIOx + C:03D7H LINE# 28 + C:03D7H LINE# 29 + C:03D7H LINE# 30 + C:03E1H LINE# 31 + C:03E4H LINE# 32 + C:03F1H LINE# 33 + C:03F4H LINE# 34 + C:03F7H LINE# 35 + C:03F7H LINE# 36 + C:03FAH LINE# 37 + C:0405H LINE# 38 + C:040CH LINE# 39 + C:0417H LINE# 40 + C:041FH LINE# 41 + C:0429H LINE# 42 + C:042EH LINE# 43 + C:043BH LINE# 44 + C:043BH LINE# 45 + C:0440H LINE# 46 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 7 + + + C:0440H LINE# 47 + C:0446H LINE# 48 + C:0451H LINE# 49 + C:0456H LINE# 50 + C:0461H LINE# 51 + C:0468H LINE# 52 + C:0472H LINE# 53 + C:0479H LINE# 54 + C:0486H LINE# 55 + C:0486H LINE# 56 + C:048BH LINE# 57 + C:048BH LINE# 58 + C:0491H LINE# 59 + C:049CH LINE# 60 + C:04A1H LINE# 61 + C:04ACH LINE# 62 + C:04B3H LINE# 63 + C:04BDH LINE# 64 + C:04C4H LINE# 65 + C:04D1H LINE# 66 + C:04D1H LINE# 67 + C:04D6H LINE# 68 + C:04D6H LINE# 69 + C:04DCH LINE# 70 + C:04E7H LINE# 71 + C:04ECH LINE# 72 + C:04F7H LINE# 73 + C:04FEH LINE# 74 + C:0508H LINE# 75 + C:050FH LINE# 76 + C:051CH LINE# 77 + C:051CH LINE# 78 + C:0521H LINE# 79 + C:0521H LINE# 80 + C:0527H LINE# 81 + C:0532H LINE# 82 + C:0537H LINE# 83 + C:0542H LINE# 84 + C:0549H LINE# 85 + C:0553H LINE# 86 + C:055AH LINE# 87 + C:0567H LINE# 88 + C:0567H LINE# 89 + C:056CH LINE# 90 + C:056CH LINE# 91 + C:0572H LINE# 92 + C:057DH LINE# 93 + C:0582H LINE# 94 + C:058DH LINE# 95 + C:0594H LINE# 96 + C:059EH LINE# 97 + C:05A5H LINE# 98 + C:05B2H LINE# 99 + C:05B2H LINE# 100 + C:05B7H LINE# 101 + C:05B7H LINE# 102 + C:05BDH LINE# 103 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 8 + + + C:05C8H LINE# 104 + C:05CDH LINE# 105 + C:05D8H LINE# 106 + C:05DFH LINE# 107 + C:05E9H LINE# 108 + C:05F0H LINE# 109 + C:05FDH LINE# 110 + C:05FDH LINE# 111 + C:0602H LINE# 112 + C:0602H LINE# 113 + C:060AH LINE# 114 + C:0615H LINE# 115 + C:061BH LINE# 116 + C:0626H LINE# 117 + C:062DH LINE# 118 + C:0637H LINE# 119 + C:063EH LINE# 120 + C:064BH LINE# 121 + C:064BH LINE# 122 + C:064DH LINE# 123 + ------- ENDPROC _GPIO_INILIZE + ------- PROC GPIO_CONFIG + ------- DO + D:0008H SYMBOL GPIO_InitStructure + ------- ENDDO + C:001EH LINE# 124 + C:001EH LINE# 125 + C:001EH LINE# 128 + C:0021H LINE# 129 + C:0024H LINE# 130 + C:002EH LINE# 131 + C:0031H LINE# 132 + C:0034H LINE# 133 + C:0039H LINE# 134 + C:003BH LINE# 135 + C:003DH LINE# 136 + C:003FH LINE# 137 + ------- ENDPROC GPIO_CONFIG + ------- ENDMOD GPIO + + ------- MODULE MAIN + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + D:00A0H PUBLIC P2 + D:00B0H PUBLIC P3 + D:00C0H PUBLIC P4 + D:00C8H PUBLIC P5 + B:00A8H.7 PUBLIC EA + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + C:0086H PUBLIC main + D:0098H PUBLIC SCON + D:0088H PUBLIC TCON + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 9 + + + D:00F0H PUBLIC B + D:00E0H PUBLIC ACC + D:00D0H PUBLIC PSW + ------- PROC MAIN + C:0086H LINE# 19 + C:0086H LINE# 20 + C:0086H LINE# 21 + C:0089H LINE# 22 + C:008CH LINE# 23 + C:008FH LINE# 24 + C:0091H LINE# 25 + C:0091H LINE# 26 + C:0091H LINE# 27 + ------- ENDPROC MAIN + ------- ENDMOD MAIN + + ------- MODULE TIMER + C:0000H SYMBOL _ICE_DUMMY_ + D:0080H PUBLIC P0 + D:0090H PUBLIC P1 + C:089EH PUBLIC timer0_int + D:00A0H PUBLIC P2 + C:0011H PUBLIC timer1_int + D:00B0H PUBLIC P3 + C:0012H PUBLIC timer2_int + D:00C0H PUBLIC P4 + C:0016H PUBLIC timer3_int + D:00C8H PUBLIC P5 + C:0017H PUBLIC timer4_int + D:00E8H PUBLIC P6 + D:00F8H PUBLIC P7 + D:00A8H PUBLIC IE + D:00B8H PUBLIC IP + D:00D8H PUBLIC CCON + D:0098H PUBLIC SCON + D:0089H PUBLIC TMOD + D:0088H PUBLIC TCON + C:00A6H PUBLIC _Timer_Inilize + D:0010H PUBLIC KILL_time + D:00AFH PUBLIC IE2 + D:00F0H PUBLIC B + D:008EH PUBLIC AUXR + D:00E0H PUBLIC ACC + B:00A8H.1 PUBLIC ET0 + B:00A8H.3 PUBLIC ET1 + D:008CH PUBLIC TH0 + D:008DH PUBLIC TH1 + D:00D6H PUBLIC TH2 + D:00D4H PUBLIC TH3 + D:00D2H PUBLIC TH4 + D:008AH PUBLIC TL0 + D:008BH PUBLIC TL1 + D:00D7H PUBLIC TL2 + D:00D5H PUBLIC TL3 + B:00B8H.1 PUBLIC PT0 + D:00D3H PUBLIC TL4 + B:00B8H.3 PUBLIC PT1 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 10 + + + B:0088H.4 PUBLIC TR0 + B:0088H.6 PUBLIC TR1 + D:00D1H PUBLIC T4T3M + C:0880H PUBLIC Timer_config + D:00B7H PUBLIC IPH + D:008FH PUBLIC INT_CLKO + D:00D0H PUBLIC PSW + ------- PROC TIMER0_INT + C:089EH LINE# 22 + C:08A0H LINE# 24 + C:08A4H LINE# 25 + C:08A4H LINE# 26 + C:08A6H LINE# 27 + C:08A6H LINE# 28 + ------- ENDPROC TIMER0_INT + ------- PROC TIMER1_INT + C:0011H LINE# 31 + C:0011H LINE# 34 + ------- ENDPROC TIMER1_INT + ------- PROC TIMER2_INT + C:0012H LINE# 37 + C:0012H LINE# 40 + ------- ENDPROC TIMER2_INT + ------- PROC TIMER3_INT + C:0016H LINE# 43 + C:0016H LINE# 46 + ------- ENDPROC TIMER3_INT + ------- PROC TIMER4_INT + C:0017H LINE# 49 + C:0017H LINE# 52 + ------- ENDPROC TIMER4_INT + ------- PROC _TIMER_INILIZE + D:0005H SYMBOL TIM + D:0001H SYMBOL TIMx + C:00A6H LINE# 62 + C:00A8H LINE# 63 + C:00A8H LINE# 64 + C:00B5H LINE# 66 + C:00BBH LINE# 67 + C:00BBH LINE# 68 + C:00BDH LINE# 69 + C:00CBH LINE# 70 + C:00CDH LINE# 71 + C:00E0H LINE# 72 + C:010CH LINE# 74 + C:011CH LINE# 75 + C:0123H LINE# 76 + C:0133H LINE# 77 + C:013AH LINE# 78 + C:0145H LINE# 79 + C:0148H LINE# 80 + C:0157H LINE# 81 + C:015AH LINE# 83 + C:016CH LINE# 84 + C:0178H LINE# 85 + C:017BH LINE# 86 + C:017BH LINE# 88 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 11 + + + C:0183H LINE# 89 + C:0183H LINE# 90 + C:0185H LINE# 91 + C:0193H LINE# 92 + C:0195H LINE# 93 + C:01A8H LINE# 94 + C:01D4H LINE# 95 + C:01E4H LINE# 96 + C:01F0H LINE# 97 + C:0200H LINE# 98 + C:0207H LINE# 99 + C:0212H LINE# 100 + C:0215H LINE# 101 + C:0224H LINE# 102 + C:0227H LINE# 104 + C:0239H LINE# 105 + C:0245H LINE# 106 + C:0248H LINE# 107 + C:0248H LINE# 109 + C:024DH LINE# 110 + C:024DH LINE# 111 + C:0250H LINE# 112 + C:025FH LINE# 113 + C:0262H LINE# 114 + C:0275H LINE# 115 + C:0280H LINE# 116 + C:0287H LINE# 117 + C:0292H LINE# 118 + C:0295H LINE# 119 + C:02A4H LINE# 120 + C:02A7H LINE# 122 + C:02B9H LINE# 123 + C:02C6H LINE# 124 + C:02C9H LINE# 125 + C:02C9H LINE# 127 + C:02CEH LINE# 128 + C:02CEH LINE# 129 + C:02D1H LINE# 130 + C:02E0H LINE# 131 + C:02E3H LINE# 132 + C:02F6H LINE# 133 + C:0301H LINE# 134 + C:0308H LINE# 135 + C:0313H LINE# 136 + C:0316H LINE# 137 + C:0325H LINE# 138 + C:0328H LINE# 140 + C:033AH LINE# 141 + C:0347H LINE# 142 + C:034AH LINE# 143 + C:034AH LINE# 145 + C:0352H LINE# 146 + C:0352H LINE# 147 + C:0355H LINE# 148 + C:0364H LINE# 149 + C:0367H LINE# 150 + C:037CH LINE# 151 + BL51 BANKED LINKER/LOCATER V6.22.2.0 04/10/2023 15:47:03 PAGE 12 + + + C:0385H LINE# 152 + C:0390H LINE# 153 + C:039FH LINE# 154 + C:03A2H LINE# 155 + C:03B1H LINE# 156 + C:03B4H LINE# 158 + C:03C4H LINE# 159 + C:03D1H LINE# 160 + C:03D4H LINE# 161 + C:03D4H LINE# 162 + C:03D6H LINE# 163 + ------- ENDPROC _TIMER_INILIZE + ------- PROC TIMER_CONFIG + ------- DO + D:0008H SYMBOL TIM_InitStructure + ------- ENDDO + C:0880H LINE# 165 + C:0880H LINE# 166 + C:0880H LINE# 168 + C:0883H LINE# 169 + C:0885H LINE# 170 + C:0888H LINE# 171 + C:088AH LINE# 172 + C:088CH LINE# 173 + C:0892H LINE# 174 + C:0895H LINE# 175 + ------- ENDPROC TIMER_CONFIG + ------- ENDMOD TIMER + + ------- MODULE ?C?CLDPTR + C:0802H PUBLIC ?C?CLDPTR + ------- ENDMOD ?C?CLDPTR + + ------- MODULE ?C?CLDOPTR + C:081BH PUBLIC ?C?CLDOPTR + ------- ENDMOD ?C?CLDOPTR + + ------- MODULE ?C?ILDOPTR + C:0848H PUBLIC ?C?ILDOPTR + ------- ENDMOD ?C?ILDOPTR + +Program Size: data=18.0 xdata=0 code=2183 +LINK/LOCATE RUN COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/main.lst b/Listings/main.lst new file mode 100644 index 0000000..56be677 --- /dev/null +++ b/Listings/main.lst @@ -0,0 +1,52 @@ +C51 COMPILER V9.60.0.0 MAIN 04/10/2023 15:47:03 PAGE 1 + + +C51 COMPILER V9.60.0.0, COMPILATION OF MODULE MAIN +OBJECT MODULE PLACED IN .\Objects\main.obj +COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\main.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEN + -D PRINT(.\Listings\main.lst) TABS(2) OBJECT(.\Objects\main.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 #include "config.h" + 14 #include "GPIO.h" + 15 #include "Exti.h" + 16 #include "timer.h" + 17 + 18 /******************** Ö÷º¯Êý***********************/ + 19 void main(void) + 20 { + 21 1 GPIO_config(); + 22 1 Exti_config(); + 23 1 Timer_config(); + 24 1 EA = 1; + 25 1 while (1) + 26 1 { + 27 2 } + 28 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 13 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Listings/timer.lst b/Listings/timer.lst new file mode 100644 index 0000000..04fb58e --- /dev/null +++ b/Listings/timer.lst @@ -0,0 +1,210 @@ +C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 1 + + +C51 COMPILER V9.60.0.0, COMPILATION OF MODULE TIMER +OBJECT MODULE PLACED IN .\Objects\timer.obj +COMPILER INVOKED BY: d:\Keil_v5\C51\BIN\C51.EXE mycode\timer.c OPTIMIZE(8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTE + -ND PRINT(.\Listings\timer.lst) TABS(2) OBJECT(.\Objects\timer.obj) + +line level source + + 1 /*---------------------------------------------------------------------*/ + 2 /* --- STC MCU Limited ------------------------------------------------*/ + 3 /* --- STC 1T Series MCU Demo Programme -------------------------------*/ + 4 /* --- Mobile: (86)13922805190 ----------------------------------------*/ + 5 /* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ + 6 /* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ + 7 /* --- Web: www.STCMCU.com --------------------------------------------*/ + 8 /* --- Web: www.STCMCUDATA.com ---------------------------------------*/ + 9 /* --- QQ: 800003751 -------------------------------------------------*/ + 10 /* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ + 11 /*---------------------------------------------------------------------*/ + 12 + 13 /************* ¹¦ÄÜ˵Ã÷ ************** + 14 + 15 ±¾ÎļþΪSTC8ϵÁеĶ¨Ê±Æ÷³õʼ»¯ºÍÖжϳÌÐò,Óû§¿ÉÒÔÔÚÕâ¸öÎļþÖÐÐÞ¸Ä×Ô¼ºÐèÒªµÄÖжϳÌÐò. + 16 + 17 ******************************************/ + 18 + 19 #include "timer.h" + 20 u8 KILL_time = 0; + 21 /********************* Timer0ÖжϺ¯Êý************************/ + 22 void timer0_int (void) interrupt TIMER0_VECTOR + 23 { + 24 1 if (KILL_time) + 25 1 { + 26 2 KILL_time--; + 27 2 } + 28 1 } + 29 + 30 /********************* Timer1ÖжϺ¯Êý************************/ + 31 void timer1_int (void) interrupt TIMER1_VECTOR + 32 { + 33 1 + 34 1 } + 35 + 36 /********************* Timer2ÖжϺ¯Êý************************/ + 37 void timer2_int (void) interrupt TIMER2_VECTOR + 38 { + 39 1 + 40 1 } + 41 + 42 /********************* Timer3ÖжϺ¯Êý************************/ + 43 void timer3_int (void) interrupt TIMER3_VECTOR + 44 { + 45 1 + 46 1 } + 47 + 48 /********************* Timer4ÖжϺ¯Êý************************/ + 49 void timer4_int (void) interrupt TIMER4_VECTOR + 50 { + 51 1 + 52 1 } + 53 + 54 + C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 2 + + 55 //======================================================================== + 56 // º¯Êý: u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) + 57 // ÃèÊö: ¶¨Ê±Æ÷³õʼ»¯³ÌÐò. + 58 // ²ÎÊý: TIMx: ½á¹¹²ÎÊý,Çë²Î¿¼timer.hÀïµÄ¶¨Òå. + 59 // ·µ»Ø: ³É¹¦·µ»Ø0, ¿Õ²Ù×÷·µ»Ø1,´íÎó·µ»Ø2. + 60 // °æ±¾: V1.0, 2012-10-22 + 61 //======================================================================== + 62 u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) + 63 { + 64 1 if(TIM > Timer4) return 1; //¿Õ²Ù×÷ + 65 1 + 66 1 if(TIM == Timer0) + 67 1 { + 68 2 Timer0_Stop(); //Í£Ö¹¼ÆÊý + 69 2 if(TIMx->TIM_Interrupt == ENABLE) Timer0_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + 70 2 else Timer0_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + 71 2 if(TIMx->TIM_Priority > Priority_3) return 2; //´íÎó + 72 2 Timer0_Priority(TIMx->TIM_Priority); //Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_ + -3 + 73 2 + 74 2 if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //´íÎó + 75 2 TMOD = (TMOD & ~0x03) | TIMx->TIM_Mode; //¹¤×÷ģʽ,0: 16λ×Ô¶¯ÖØ×°, 1: 16λ¶¨Ê±/¼ÆÊý, 2: 8λ×Ô¶¯ÖØ×°, 3: + - ²»¿ÉÆÁ±Î16λ×Ô¶¯ÖØ×° + 76 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer0_12T(); //12T + 77 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer0_1T(); //1T + 78 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer0_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + 79 2 else Timer0_AsTimer(); //¶¨Ê± + 80 2 if(TIMx->TIM_ClkOut == ENABLE) Timer0_CLKO_Enable(); //Êä³öʱÖÓ + 81 2 else Timer0_CLKO_Disable(); //²»Êä³öʱÖÓ + 82 2 + 83 2 T0_Load(TIMx->TIM_Value); + 84 2 if(TIMx->TIM_Run == ENABLE) Timer0_Run(); //¿ªÊ¼ÔËÐÐ + 85 2 return 0; //³É¹¦ + 86 2 } + 87 1 + 88 1 if(TIM == Timer1) + 89 1 { + 90 2 Timer1_Stop(); //Í£Ö¹¼ÆÊý + 91 2 if(TIMx->TIM_Interrupt == ENABLE) Timer1_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + 92 2 else Timer1_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + 93 2 if(TIMx->TIM_Priority > Priority_3) return 2; //´íÎó + 94 2 Timer1_Priority(TIMx->TIM_Priority); //Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_ + -3 + 95 2 if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //´íÎó + 96 2 TMOD = (TMOD & ~0x30) | (TIMx->TIM_Mode<<4); //¹¤×÷ģʽ,0: 16λ×Ô¶¯ÖØ×°, 1: 16λ¶¨Ê±/¼ÆÊý, 2: 8λ×Ô¶¯ÖØ× + -°, 3: Í£Ö¹¹¤×÷ + 97 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer1_12T(); //12T + 98 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer1_1T(); //1T + 99 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer1_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + 100 2 else Timer1_AsTimer(); //¶¨Ê± + 101 2 if(TIMx->TIM_ClkOut == ENABLE) Timer1_CLKO_Enable(); //Êä³öʱÖÓ + 102 2 else Timer1_CLKO_Disable(); //²»Êä³öʱÖÓ + 103 2 + 104 2 T1_Load(TIMx->TIM_Value); + 105 2 if(TIMx->TIM_Run == ENABLE) Timer1_Run(); //¿ªÊ¼ÔËÐÐ + 106 2 return 0; //³É¹¦ + 107 2 } + 108 1 + 109 1 if(TIM == Timer2) //Timer2,¹Ì¶¨Îª16λ×Ô¶¯ÖØ×°, ÖжÏÎÞÓÅÏȼ¶ + 110 1 { + 111 2 Timer2_Stop(); //Í£Ö¹¼ÆÊý + 112 2 if(TIMx->TIM_Interrupt == ENABLE) Timer2_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 3 + + 113 2 else Timer2_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + 114 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + 115 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer2_12T(); //12T + 116 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer2_1T(); //1T + 117 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer2_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + 118 2 else Timer2_AsTimer(); //¶¨Ê± + 119 2 if(TIMx->TIM_ClkOut == ENABLE) Timer2_CLKO_Enable(); //Êä³öʱÖÓ + 120 2 else Timer2_CLKO_Disable(); //²»Êä³öʱÖÓ + 121 2 + 122 2 T2_Load(TIMx->TIM_Value); + 123 2 if(TIMx->TIM_Run == ENABLE) Timer2_Run(); //¿ªÊ¼ÔËÐÐ + 124 2 return 0; //³É¹¦ + 125 2 } + 126 1 + 127 1 if(TIM == Timer3) //Timer3,¹Ì¶¨Îª16λ×Ô¶¯ÖØ×°, ÖжÏÎÞÓÅÏȼ¶ + 128 1 { + 129 2 Timer3_Stop(); //Í£Ö¹¼ÆÊý + 130 2 if(TIMx->TIM_Interrupt == ENABLE) Timer3_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + 131 2 else Timer3_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + 132 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + 133 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer3_12T(); //12T + 134 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer3_1T(); //1T + 135 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer3_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + 136 2 else Timer3_AsTimer(); //¶¨Ê± + 137 2 if(TIMx->TIM_ClkOut == ENABLE) Timer3_CLKO_Enable(); //Êä³öʱÖÓ + 138 2 else Timer3_CLKO_Disable(); //²»Êä³öʱÖÓ + 139 2 + 140 2 T3_Load(TIMx->TIM_Value); + 141 2 if(TIMx->TIM_Run == ENABLE) Timer3_Run(); //¿ªÊ¼ÔËÐÐ + 142 2 return 0; //³É¹¦ + 143 2 } + 144 1 + 145 1 if(TIM == Timer4) //Timer3,¹Ì¶¨Îª16λ×Ô¶¯ÖØ×°, ÖжÏÎÞÓÅÏȼ¶ + 146 1 { + 147 2 Timer4_Stop(); //Í£Ö¹¼ÆÊý + 148 2 if(TIMx->TIM_Interrupt == ENABLE) Timer4_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + 149 2 else Timer4_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + 150 2 if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + 151 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer4_12T(); //12T + 152 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer4_1T(); //1T + 153 2 if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer4_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + 154 2 else Timer4_AsTimer(); //¶¨Ê± + 155 2 if(TIMx->TIM_ClkOut == ENABLE) Timer4_CLKO_Enable(); //Êä³öʱÖÓ + 156 2 else Timer4_CLKO_Disable(); //²»Êä³öʱÖÓ + 157 2 + 158 2 T4_Load(TIMx->TIM_Value); + 159 2 if(TIMx->TIM_Run == ENABLE) Timer4_Run(); //¿ªÊ¼ÔËÐÐ + 160 2 return 0; //³É¹¦ + 161 2 } + 162 1 return 2; //´íÎó + 163 1 } + 164 /************************ ?¡§?¡À?¡Â???? ****************************/ + 165 void Timer_config(void) + 166 { + 167 1 TIM_InitTypeDef TIM_InitStructure; + 168 1 TIM_InitStructure.TIM_Mode = TIM_16BitAutoReload; + 169 1 TIM_InitStructure.TIM_Priority = Priority_0; + 170 1 TIM_InitStructure.TIM_Interrupt = ENABLE; + 171 1 TIM_InitStructure.TIM_ClkSource = TIM_CLOCK_1T; + 172 1 TIM_InitStructure.TIM_ClkOut = DISABLE; + 173 1 TIM_InitStructure.TIM_Value = 65536UL - (MAIN_Fosc / 1000UL); + 174 1 TIM_InitStructure.TIM_Run = ENABLE; + C51 COMPILER V9.60.0.0 TIMER 04/10/2023 15:47:03 PAGE 4 + + 175 1 Timer_Inilize(Timer0,&TIM_InitStructure); + 176 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 862 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = 1 8 + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Objects/Exti.__i b/Objects/Exti.__i new file mode 100644 index 0000000..28e691a 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+
µVision Build Log

+
Tool Versions:

+IDE-Version: ¦ÌVision V5.27.1.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: xx xx, xx, LIC=WH7DL-0DZI4-3A0DP-MA9EC-R17VA-4MPD4
+ 
+Tool Versions:
+Toolchain:       PK51 Prof. Developers Kit  Version: 9.60.0.0
+Toolchain Path:  d:\Keil_v5\C51\BIN
+C Compiler:      C51.exe V9.60.0.0
+Assembler:       A51.exe V8.2.7.0
+Linker/Locator:  BL51.exe V6.22.2.0
+Library Manager: LIB51.exe V4.30.1.0
+Hex Converter:   OH51.exe V2.7.0.0
+CPU DLL:         S8051.DLL V3.122.0.0
+Dialog DLL:      DP51.DLL V2.67.0.0 
+
Project:

+d:\Users\User\Documents\peek250kill control\kill_control.uvproj
+Project File Date:  04/10/2023
+
+
Output:

+Build target 'Target 1'
+compiling Exti.c...
+compiling GPIO.c...
+compiling main.c...
+compiling timer.c...
+linking...
+Program Size: data=18.0 xdata=0 code=2183
+creating hex file from ".\Objects\kill_control"...
+".\Objects\kill_control" - 0 Error(s), 0 Warning(s).
+Build Time Elapsed:  00:00:00
+
+ + diff --git a/Objects/kill_control.hex b/Objects/kill_control.hex new file mode 100644 index 0000000..7e28a31 --- /dev/null +++ b/Objects/kill_control.hex @@ -0,0 +1,163 @@ +:030000000207767E +:0C077600787FE4F6D8FD7581100207BD05 +:0300030002006692 +:10006600C0E030B20CE510700BB290B291B2928043 +:0700760003751032D0E032E7 +:0300130002000ADE +:01000A0032C3 +:0300530002000E9A +:01000E0032BF +:03005B0002000F91 +:01000F0032BE +:0300830002001068 +:0100100032BD +:10064E00EFD394047480948040037F0122EF706195 +:10065E00C28990000212081B64017004D2A88002A5 +:10066E00C2A890000112081BFED3940374809480DC +:10067E0040037F0222EEFD7C00700553B7FEC2B828 +:10068E00ED64014C700553B7FED2B8ED64024C70A8 +:10069E000543B701C2B8ED64034C700543B701D2F0 +:1006AE00B812080264017004D2888002C2887F00EA +:1006BE0022EF64017061C28B90000212081B64016C +:1006CE007004D2AA8002C2AA90000112081BFED3A7 +:1006DE0094037480948040037F0222EEFD7C0070B0 +:1006EE000553B7FBC2BAED64014C700553B7FBD28C +:1006FE00BAED64024C700543B704C2BAED64034C04 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+TO ".\Objects\kill_control" +PRINT(".\Listings\kill_control.m51") RAMSIZE(256) diff --git a/Objects/main.__i b/Objects/main.__i new file mode 100644 index 0000000..442891a --- /dev/null +++ b/Objects/main.__i @@ -0,0 +1 @@ +"mycode\main.c" OPTIMIZE (8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEND PRINT(.\Listings\main.lst) TABS (2) OBJECT(.\Objects\main.obj) \ No newline at end of file diff --git a/Objects/main.obj b/Objects/main.obj new file mode 100644 index 0000000000000000000000000000000000000000..5f0af087b8751698a48fb8983f67c8a6b99546f6 GIT binary patch literal 105246 zcmbt-2Vhjyw)Q{>RRk3aHc)I>=bV{If(<5<2^pCr$C(KrqGLh=L_&fo3ijT;_TGE% zdhNaU-h1!8UCY&f?Q_mL^G(8h?|=W#dshSU?Y+Z74K)*;OsXL#eNbBgLbq)@FDt~#bznHo6x;p2#FW7S7 z;LwnBlg(StZR%<3?s5M)x29`e-{Q7TnQ2K|+afy_Uew;vF;M`$-CZ5tx6IAv5>-p( z*OqmIL+LlpX$x-9+B@=l#^wr*=B7I5&21MzduNZC}CypBRjpT-w{N6IJ|g$J7NGqE-HH!M*K^+q%uv20cc<(f`xR!NWsC>f@<~ zzXv@#W{uFGkoo`6=+Nk?PG+k4bN3(P#wSCA<DnC4Keu&9z*M|lTPR8X=J~w|-AwT@b{7@-BTp>TClJdjt<_AZ9cs*1$Bq3jG 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literal 0 HcmV?d00001 diff --git a/Objects/timer.__i b/Objects/timer.__i new file mode 100644 index 0000000..695df70 --- /dev/null +++ b/Objects/timer.__i @@ -0,0 +1 @@ +"mycode\timer.c" OPTIMIZE (8,SPEED) BROWSE INCDIR(.\myinc) DEBUG OBJECTEXTEND PRINT(.\Listings\timer.lst) TABS (2) OBJECT(.\Objects\timer.obj) \ No newline at end of file diff --git a/Objects/timer.obj b/Objects/timer.obj new file mode 100644 index 0000000000000000000000000000000000000000..f51be806cb8e2d3478389e77822d738adddc1212 GIT binary patch literal 111985 zcmce<2Xs``7dLuSXrclN_JSZP7M!^=lLQ+ilL;A_B;(8kP|+a`iG&bSP;3-M#a>YC zy#(AKPmM-`BS+1d z-!iwgZF+C}oVM<9Eu%&@Bs1~4_&%}iDt1gKW3lS7BdbykQ`51L@%m_WJhk1p>2v0{ zceacjSskltoHVkbYR_0S6PuQa)mM*9rsDM(`in$+Pj7qY0X=T59X-8cM`kLk(%ac% zT>$-2L-T=cExqzLbDIwwYgxZN5NcijKfWrm?z}tHx^8Y?i_Jd{aXaL;HLKYAlq#v1 z-q_RD-D959tLL`#&1vhTwz}HdX4{d#?Dme1ku7sOd%Nd$IK!DvrJ3yqj3apI1+k`G z{@=pWnP|l!^ch!MY$e_}zj3qHU8YZNYwyU;i%h3!o*wUPnchzAwRiT6o3&Z-AgdqE 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+;------------------------------------------------------------------------------ +; STARTUP.A51: This code is executed after processor reset. +; +; To translate this file use A51 with the following invocation: +; +; A51 STARTUP.A51 +; +; To link the modified STARTUP.OBJ file to your application use the following +; Lx51 invocation: +; +; Lx51 your object file list, STARTUP.OBJ controls +; +;------------------------------------------------------------------------------ +; +; User-defined Power-On Initialization of Memory +; +; With the following EQU statements the initialization of memory +; at processor reset can be defined: +; +; IDATALEN: IDATA memory size <0x0-0x100> +; Note: The absolute start-address of IDATA memory is always 0 +; The IDATA space overlaps physically the DATA and BIT areas. +IDATALEN EQU 80H +; +; XDATASTART: XDATA memory start address <0x0-0xFFFF> +; The absolute start address of XDATA memory +XDATASTART EQU 0 +; +; XDATALEN: XDATA memory size <0x0-0xFFFF> +; The length of XDATA memory in bytes. +XDATALEN EQU 0 +; +; PDATASTART: PDATA memory start address <0x0-0xFFFF> +; The absolute start address of PDATA memory +PDATASTART EQU 0H +; +; PDATALEN: PDATA memory size <0x0-0xFF> +; The length of PDATA memory in bytes. +PDATALEN EQU 0H +; +; +;------------------------------------------------------------------------------ +; +; Reentrant Stack Initialization +; +; The following EQU statements define the stack pointer for reentrant +; functions and initialized it: +; +; Stack Space for reentrant functions in the SMALL model. +; IBPSTACK: Enable SMALL model reentrant stack +; Stack space for reentrant functions in the SMALL model. +IBPSTACK EQU 0 ; set to 1 if small reentrant is used. +; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> +; Set the top of the stack to the highest location. +IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +; Stack Space for reentrant functions in the LARGE model. +; XBPSTACK: Enable LARGE model reentrant stack +; Stack space for reentrant functions in the LARGE model. +XBPSTACK EQU 0 ; set to 1 if large reentrant is used. +; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 +; +; +; Stack Space for reentrant functions in the COMPACT model. +; PBPSTACK: Enable COMPACT model reentrant stack +; Stack space for reentrant functions in the COMPACT model. +PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. +; +; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +;------------------------------------------------------------------------------ +; +; Memory Page for Using the Compact Model with 64 KByte xdata RAM +; Compact Model Page Definition +; +; Define the XDATA page used for PDATA variables. +; PPAGE must conform with the PPAGE set in the linker invocation. +; +; Enable pdata memory page initalization +PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. +; +; PPAGE number <0x0-0xFF> +; uppermost 256-byte address of the page used for PDATA variables. +PPAGE EQU 0 +; +; SFR address which supplies uppermost address byte <0x0-0xFF> +; most 8051 variants use P2 as uppermost address byte +PPAGE_SFR DATA 0A0H +; +; +;------------------------------------------------------------------------------ + +; Standard SFR Symbols +ACC DATA 0E0H +B DATA 0F0H +SP DATA 81H +DPL DATA 82H +DPH DATA 83H + + NAME ?C_STARTUP + + +?C_C51STARTUP SEGMENT CODE +?STACK SEGMENT IDATA + + RSEG ?STACK + DS 1 + + EXTRN CODE (?C_START) + PUBLIC ?C_STARTUP + + CSEG AT 0 +?C_STARTUP: LJMP STARTUP1 + + RSEG ?C_C51STARTUP + +STARTUP1: + +IF IDATALEN <> 0 + MOV R0,#IDATALEN - 1 + CLR A +IDATALOOP: MOV @R0,A + DJNZ R0,IDATALOOP +ENDIF + +IF XDATALEN <> 0 + MOV DPTR,#XDATASTART + MOV R7,#LOW (XDATALEN) + IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE + MOV R6,#HIGH (XDATALEN) + ENDIF + CLR A +XDATALOOP: MOVX @DPTR,A + INC DPTR + DJNZ R7,XDATALOOP + DJNZ R6,XDATALOOP +ENDIF + +IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE +ENDIF + +IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A +PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP +ENDIF + +IF IBPSTACK <> 0 +EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP +ENDIF + +IF XBPSTACK <> 0 +EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP +ENDIF + +IF PBPSTACK <> 0 +EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP +ENDIF + + MOV SP,#?STACK-1 + +; This code is required if you use L51_BANK.A51 with Banking Mode 4 +; Code Banking +; Select Bank 0 for L51_BANK.A51 Mode 4 +#if 0 +; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4. +EXTRN CODE (?B_SWITCH0) + CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 +#endif +; + LJMP ?C_START + + END diff --git a/kill_control.uvgui.User b/kill_control.uvgui.User new file mode 100644 index 0000000..28b821c --- /dev/null +++ b/kill_control.uvgui.User @@ -0,0 +1,1914 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x0 + MCS-51 + + 35000000 + + 1 + 1 + 1 + 0 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\STARTUP.A51 + STARTUP.A51 + 0 + 0 + + + + + mycode + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + .\mycode\Exti.c + Exti.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + .\mycode\GPIO.c + GPIO.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\mycode\main.c + main.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + .\mycode\timer.c + timer.c + 0 + 0 + + + + diff --git a/kill_control.uvproj b/kill_control.uvproj new file mode 100644 index 0000000..8d02049 --- /dev/null +++ b/kill_control.uvproj @@ -0,0 +1,415 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x0 + MCS-51 + 0 + + + STC8H1K28 Series + STC + IRAM(0-0xFF) XRAM(0-0x03FF) IROM(0-0x6FF8) CLOCK(35000000) MODP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 63268 + STC8.H + + + + + + + + + + + 0 + 0 + + + + STC\ + STC\ + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + kill_control + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pDP8051 + S8051.DLL + + TP51.DLL + -p51 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x6ff9 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x400 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + + + .\myinc + + + + 0 + 1 + 0 + 0 + + + + + + + + + 0 + 0 + 1 + 0 + 2 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Source Group 1 + + + STARTUP.A51 + 2 + .\STARTUP.A51 + + + + + mycode + + + Exti.c + 1 + .\mycode\Exti.c + + + GPIO.c + 1 + .\mycode\GPIO.c + + + main.c + 1 + .\mycode\main.c + + + timer.c + 1 + .\mycode\timer.c + + + + + + + + diff --git a/mycode/Exti.c b/mycode/Exti.c new file mode 100644 index 0000000..2d6fc4b --- /dev/null +++ b/mycode/Exti.c @@ -0,0 +1,143 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ +/*---------------------------------------------------------------------*/ + +/************* ¹¦ÄÜ˵Ã÷ ************** + +±¾ÎļþΪSTC8ϵÁеÄÍâÖжϳõʼ»¯ºÍÖжϳÌÐò,Óû§¿ÉÒÔÔÚÕâ¸öÎļþÖÐÐÞ¸Ä×Ô¼ºÐèÒªµÄÖжϳÌÐò. + +******************************************/ + +#include "Exti.h" + +/************* Íⲿº¯ÊýºÍ±äÁ¿ÉùÃ÷ *****************/ + +/********************* INT0ÖжϺ¯Êý *************************/ +void Ext_INT0(void) interrupt INT0_VECTOR // ½øÖжÏʱÒѾ­Çå³ý±êÖ¾ +{ + if (kill_gpio) + { + if (KILL_time == 0) + { + power1_gpio = !power1_gpio; + power2_gpio = !power2_gpio; + power3_gpio = !power3_gpio; + } + } + else + { + KILL_time = 50; + } +} + +/********************* INT1ÖжϺ¯Êý *************************/ +void Ext_INT1(void) interrupt INT1_VECTOR // ½øÖжÏʱÒѾ­Çå³ý±êÖ¾ +{ +} + +/********************* INT2ÖжϺ¯Êý *************************/ +void Ext_INT2(void) interrupt INT2_VECTOR // +{ +} + +/********************* INT3ÖжϺ¯Êý *************************/ +void Ext_INT3(void) interrupt INT3_VECTOR +{ +} + +/********************* INT4ÖжϺ¯Êý *************************/ +void Ext_INT4(void) interrupt INT4_VECTOR +{ +} + +//======================================================================== +// º¯Êý: u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx) +// ÃèÊö: ÍⲿÖжϳõʼ»¯³ÌÐò. +// ²ÎÊý: INTx: ½á¹¹²ÎÊý,Çë²Î¿¼Exti.hÀïµÄ¶¨Òå. +// ·µ»Ø: ³É¹¦·µ»Ø0, ¿Õ²Ù×÷·µ»Ø1,´íÎó·µ»Ø2. +// °æ±¾: V1.0, 2012-10-22 +//======================================================================== +u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx) +{ + if (EXT > EXT_INT4) + return 1; // ¿Õ²Ù×÷ + + if (EXT == EXT_INT0) // ÍâÖжÏ0 + { + IE0 = 0; // ÍâÖжÏ0±ê־λ + if (INTx->EXTI_Interrupt == ENABLE) + EX0 = 1; // ÔÊÐíÖÐ¶Ï + else + EX0 = 0; // ½ûÖ¹ÖÐ¶Ï + if (INTx->EXTI_Priority > Priority_3) + return 2; // ´íÎó + INT0_Priority(INTx->EXTI_Priority); // Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_3 + if (INTx->EXTI_Mode == EXT_MODE_Fall) + IT0 = 1; // ϽµÑØÖÐ¶Ï + else + IT0 = 0; // ÉÏÉý,ϽµÑØÖÐ¶Ï + return 0; // ³É¹¦ + } + + if (EXT == EXT_INT1) // ÍâÖжÏ1 + { + IE1 = 0; // ÍâÖжÏ1±ê־λ + if (INTx->EXTI_Interrupt == ENABLE) + EX1 = 1; // ÔÊÐíÖÐ¶Ï + else + EX1 = 0; // ½ûÖ¹ÖÐ¶Ï + if (INTx->EXTI_Priority > Priority_3) + return 2; // ´íÎó + INT1_Priority(INTx->EXTI_Priority); // Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_3 + if (INTx->EXTI_Mode == EXT_MODE_Fall) + IT1 = 1; // ϽµÑØÖÐ¶Ï + else + IT1 = 0; // ÉÏÉý,ϽµÑØÖÐ¶Ï + return 0; // ³É¹¦ + } + + if (EXT == EXT_INT2) // ÍâÖжÏ2, ¹Ì¶¨ÎªÏ½µÑصÍÓÅÏȼ¶ÖÐ¶Ï + { + if (INTx->EXTI_Interrupt == ENABLE) + INT_CLKO |= (1 << 4); // ÔÊÐíÖÐ¶Ï + else + INT_CLKO &= ~(1 << 4); // ½ûÖ¹ÖÐ¶Ï + return 0; // ³É¹¦ + } + + if (EXT == EXT_INT3) // ÍâÖжÏ3, ¹Ì¶¨ÎªÏ½µÑصÍÓÅÏȼ¶ÖÐ¶Ï + { + if (INTx->EXTI_Interrupt == ENABLE) + INT_CLKO |= (1 << 5); // ÔÊÐíÖÐ¶Ï + else + INT_CLKO &= ~(1 << 5); // ½ûÖ¹ÖÐ¶Ï + return 0; // ³É¹¦ + } + + if (EXT == EXT_INT4) // ÍâÖжÏ4, ¹Ì¶¨ÎªÏ½µÑصÍÓÅÏȼ¶ÖÐ¶Ï + { + if (INTx->EXTI_Interrupt == ENABLE) + INT_CLKO |= (1 << 6); // ÔÊÐíÖÐ¶Ï + else + INT_CLKO &= ~(1 << 6); // ½ûÖ¹ÖÐ¶Ï + return 0; // ³É¹¦ + } + return 2; // ʧ°Ü +} +void Exti_config(void) +{ + EXTI_InitTypeDef Exti_InitStructure; // ½á¹¹¶¨Òå + + Exti_InitStructure.EXTI_Interrupt = ENABLE; // ÖжÏʹÄÜ, ENABLE»òDISABLE + Exti_InitStructure.EXTI_Mode = EXT_MODE_RiseFall; // ÖжÏģʽ, EXT_MODE_RiseFall,EXT_MODE_Fall + Exti_InitStructure.EXTI_Priority = Priority_0; // Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_3 + Ext_Inilize(EXT_INT0, &Exti_InitStructure); // ³õʼ»¯ +} \ No newline at end of file diff --git a/mycode/GPIO.c b/mycode/GPIO.c new file mode 100644 index 0000000..974229c --- /dev/null +++ b/mycode/GPIO.c @@ -0,0 +1,137 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ +/*---------------------------------------------------------------------*/ + +/*************** ¹¦ÄÜ˵Ã÷ **************** + +±¾ÎļþΪSTC8ϵÁеĶ˿ڳõʼ»¯³ÌÐò,Óû§¼¸ºõ¿ÉÒÔ²»ÐÞ¸ÄÕâ¸ö³ÌÐò. + +******************************************/ + +#include "GPIO.h" + +//======================================================================== +// º¯Êý: u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) +// ÃèÊö: ³õʼ»¯IO¿Ú. +// ²ÎÊý: GPIOx: ½á¹¹²ÎÊý,Çë²Î¿¼timer.hÀïµÄ¶¨Òå. +// ·µ»Ø: ³É¹¦·µ»Ø0, ¿Õ²Ù×÷·µ»Ø1,´íÎó·µ»Ø2. +// °æ±¾: V1.0, 2012-10-22 +//======================================================================== +u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx) +{ + if (GPIO > GPIO_P7) + return 1; // ¿Õ²Ù×÷ + if (GPIOx->Mode > GPIO_OUT_PP) + return 2; // ´íÎó + if (GPIO == GPIO_P0) + { + if (GPIOx->Mode == GPIO_PullUp) + P0M1 &= ~GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P0M1 |= GPIOx->Pin, P0M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P0M1 |= GPIOx->Pin, P0M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P0M1 &= ~GPIOx->Pin, P0M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P1) + { + if (GPIOx->Mode == GPIO_PullUp) + P1M1 &= ~GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P1M1 |= GPIOx->Pin, P1M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P1M1 |= GPIOx->Pin, P1M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P1M1 &= ~GPIOx->Pin, P1M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P2) + { + if (GPIOx->Mode == GPIO_PullUp) + P2M1 &= ~GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P2M1 |= GPIOx->Pin, P2M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P2M1 |= GPIOx->Pin, P2M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P2M1 &= ~GPIOx->Pin, P2M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P3) + { + if (GPIOx->Mode == GPIO_PullUp) + P3M1 &= ~GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P3M1 |= GPIOx->Pin, P3M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P3M1 |= GPIOx->Pin, P3M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P3M1 &= ~GPIOx->Pin, P3M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P4) + { + if (GPIOx->Mode == GPIO_PullUp) + P4M1 &= ~GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P4M1 |= GPIOx->Pin, P4M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P4M1 |= GPIOx->Pin, P4M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P4M1 &= ~GPIOx->Pin, P4M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P5) + { + if (GPIOx->Mode == GPIO_PullUp) + P5M1 &= ~GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P5M1 |= GPIOx->Pin, P5M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P5M1 |= GPIOx->Pin, P5M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P5M1 &= ~GPIOx->Pin, P5M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P6) + { + if (GPIOx->Mode == GPIO_PullUp) + P6M1 &= ~GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P6M1 |= GPIOx->Pin, P6M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P6M1 |= GPIOx->Pin, P6M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P6M1 &= ~GPIOx->Pin, P6M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + if (GPIO == GPIO_P7) + { + if (GPIOx->Mode == GPIO_PullUp) + P7M1 &= ~GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // ÉÏÀ­×¼Ë«Ïò¿Ú + if (GPIOx->Mode == GPIO_HighZ) + P7M1 |= GPIOx->Pin, P7M0 &= ~GPIOx->Pin; // ¸¡¿ÕÊäÈë + if (GPIOx->Mode == GPIO_OUT_OD) + P7M1 |= GPIOx->Pin, P7M0 |= GPIOx->Pin; // ¿ªÂ©Êä³ö + if (GPIOx->Mode == GPIO_OUT_PP) + P7M1 &= ~GPIOx->Pin, P7M0 |= GPIOx->Pin; // ÍÆÍìÊä³ö + } + return 0; // ³É¹¦ +} +void GPIO_config(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; // ½á¹¹¶¨Òå + + GPIO_InitStructure.Pin = GPIO_Pin_2; // Ö¸¶¨Òª³õʼ»¯µÄIO, GPIO_Pin_0 ~ GPIO_Pin_7, »ò²Ù×÷ + GPIO_InitStructure.Mode = GPIO_PullUp; // Ö¸¶¨IOµÄÊäÈë»òÊä³ö·½Ê½,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P3, &GPIO_InitStructure); // ³õʼ»¯ + GPIO_InitStructure.Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2; // Ö¸¶¨Òª³õʼ»¯µÄIO, GPIO_Pin_0 ~ GPIO_Pin_7, »ò²Ù×÷ + GPIO_InitStructure.Mode = GPIO_OUT_PP; // Ö¸¶¨IOµÄÊäÈë»òÊä³ö·½Ê½,GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + GPIO_Inilize(GPIO_P1, &GPIO_InitStructure); // ³õʼ»¯ + power1_gpio = 0; + power2_gpio = 0; + power3_gpio = 0; +} \ No newline at end of file diff --git a/mycode/main.c b/mycode/main.c new file mode 100644 index 0000000..a4d0816 --- /dev/null +++ b/mycode/main.c @@ -0,0 +1,28 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ +/*---------------------------------------------------------------------*/ + +#include "config.h" +#include "GPIO.h" +#include "Exti.h" +#include "timer.h" + +/******************** Ö÷º¯Êý***********************/ +void main(void) +{ + GPIO_config(); + Exti_config(); + Timer_config(); + EA = 1; + while (1) + { + } +} diff --git a/mycode/timer.c b/mycode/timer.c new file mode 100644 index 0000000..292aa47 --- /dev/null +++ b/mycode/timer.c @@ -0,0 +1,176 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ +/*---------------------------------------------------------------------*/ + +/************* ¹¦ÄÜ˵Ã÷ ************** + +±¾ÎļþΪSTC8ϵÁеĶ¨Ê±Æ÷³õʼ»¯ºÍÖжϳÌÐò,Óû§¿ÉÒÔÔÚÕâ¸öÎļþÖÐÐÞ¸Ä×Ô¼ºÐèÒªµÄÖжϳÌÐò. + +******************************************/ + +#include "timer.h" +u8 KILL_time = 0; +/********************* Timer0ÖжϺ¯Êý************************/ +void timer0_int (void) interrupt TIMER0_VECTOR +{ + if (KILL_time) + { + KILL_time--; + } +} + +/********************* Timer1ÖжϺ¯Êý************************/ +void timer1_int (void) interrupt TIMER1_VECTOR +{ + +} + +/********************* Timer2ÖжϺ¯Êý************************/ +void timer2_int (void) interrupt TIMER2_VECTOR +{ + +} + +/********************* Timer3ÖжϺ¯Êý************************/ +void timer3_int (void) interrupt TIMER3_VECTOR +{ + +} + +/********************* Timer4ÖжϺ¯Êý************************/ +void timer4_int (void) interrupt TIMER4_VECTOR +{ + +} + + +//======================================================================== +// º¯Êý: u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) +// ÃèÊö: ¶¨Ê±Æ÷³õʼ»¯³ÌÐò. +// ²ÎÊý: TIMx: ½á¹¹²ÎÊý,Çë²Î¿¼timer.hÀïµÄ¶¨Òå. +// ·µ»Ø: ³É¹¦·µ»Ø0, ¿Õ²Ù×÷·µ»Ø1,´íÎó·µ»Ø2. +// °æ±¾: V1.0, 2012-10-22 +//======================================================================== +u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx) +{ + if(TIM > Timer4) return 1; //¿Õ²Ù×÷ + + if(TIM == Timer0) + { + Timer0_Stop(); //Í£Ö¹¼ÆÊý + if(TIMx->TIM_Interrupt == ENABLE) Timer0_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + else Timer0_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + if(TIMx->TIM_Priority > Priority_3) return 2; //´íÎó + Timer0_Priority(TIMx->TIM_Priority); //Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_3 + + if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //´íÎó + TMOD = (TMOD & ~0x03) | TIMx->TIM_Mode; //¹¤×÷ģʽ,0: 16λ×Ô¶¯ÖØ×°, 1: 16λ¶¨Ê±/¼ÆÊý, 2: 8λ×Ô¶¯ÖØ×°, 3: ²»¿ÉÆÁ±Î16λ×Ô¶¯ÖØ×° + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer0_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer0_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer0_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + else Timer0_AsTimer(); //¶¨Ê± + if(TIMx->TIM_ClkOut == ENABLE) Timer0_CLKO_Enable(); //Êä³öʱÖÓ + else Timer0_CLKO_Disable(); //²»Êä³öʱÖÓ + + T0_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer0_Run(); //¿ªÊ¼ÔËÐÐ + return 0; //³É¹¦ + } + + if(TIM == Timer1) + { + Timer1_Stop(); //Í£Ö¹¼ÆÊý + if(TIMx->TIM_Interrupt == ENABLE) Timer1_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + else Timer1_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + if(TIMx->TIM_Priority > Priority_3) return 2; //´íÎó + Timer1_Priority(TIMx->TIM_Priority); //Ö¸¶¨ÖжÏÓÅÏȼ¶(µÍµ½¸ß) Priority_0,Priority_1,Priority_2,Priority_3 + if(TIMx->TIM_Mode >= TIM_16BitAutoReloadNoMask) return 2; //´íÎó + TMOD = (TMOD & ~0x30) | (TIMx->TIM_Mode<<4); //¹¤×÷ģʽ,0: 16λ×Ô¶¯ÖØ×°, 1: 16λ¶¨Ê±/¼ÆÊý, 2: 8λ×Ô¶¯ÖØ×°, 3: Í£Ö¹¹¤×÷ + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer1_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer1_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer1_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + else Timer1_AsTimer(); //¶¨Ê± + if(TIMx->TIM_ClkOut == ENABLE) Timer1_CLKO_Enable(); //Êä³öʱÖÓ + else Timer1_CLKO_Disable(); //²»Êä³öʱÖÓ + + T1_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer1_Run(); //¿ªÊ¼ÔËÐÐ + return 0; //³É¹¦ + } + + if(TIM == Timer2) //Timer2,¹Ì¶¨Îª16λ×Ô¶¯ÖØ×°, ÖжÏÎÞÓÅÏȼ¶ + { + Timer2_Stop(); //Í£Ö¹¼ÆÊý + if(TIMx->TIM_Interrupt == ENABLE) Timer2_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + else Timer2_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer2_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer2_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer2_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + else Timer2_AsTimer(); //¶¨Ê± + if(TIMx->TIM_ClkOut == ENABLE) Timer2_CLKO_Enable(); //Êä³öʱÖÓ + else Timer2_CLKO_Disable(); //²»Êä³öʱÖÓ + + T2_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer2_Run(); //¿ªÊ¼ÔËÐÐ + return 0; //³É¹¦ + } + + if(TIM == Timer3) //Timer3,¹Ì¶¨Îª16λ×Ô¶¯ÖØ×°, ÖжÏÎÞÓÅÏȼ¶ + { + Timer3_Stop(); //Í£Ö¹¼ÆÊý + if(TIMx->TIM_Interrupt == ENABLE) Timer3_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + else Timer3_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer3_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer3_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer3_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + else Timer3_AsTimer(); //¶¨Ê± + if(TIMx->TIM_ClkOut == ENABLE) Timer3_CLKO_Enable(); //Êä³öʱÖÓ + else Timer3_CLKO_Disable(); //²»Êä³öʱÖÓ + + T3_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer3_Run(); //¿ªÊ¼ÔËÐÐ + return 0; //³É¹¦ + } + + if(TIM == Timer4) //Timer3,¹Ì¶¨Îª16λ×Ô¶¯ÖØ×°, ÖжÏÎÞÓÅÏȼ¶ + { + Timer4_Stop(); //Í£Ö¹¼ÆÊý + if(TIMx->TIM_Interrupt == ENABLE) Timer4_InterruptEnable(); //ÔÊÐíÖÐ¶Ï + else Timer4_InterruptDisable(); //½ûÖ¹ÖÐ¶Ï + if(TIMx->TIM_ClkSource > TIM_CLOCK_Ext) return 2; + if(TIMx->TIM_ClkSource == TIM_CLOCK_12T) Timer4_12T(); //12T + if(TIMx->TIM_ClkSource == TIM_CLOCK_1T) Timer4_1T(); //1T + if(TIMx->TIM_ClkSource == TIM_CLOCK_Ext) Timer4_AsCounter(); //¶ÔÍâ¼ÆÊý»ò·ÖƵ + else Timer4_AsTimer(); //¶¨Ê± + if(TIMx->TIM_ClkOut == ENABLE) Timer4_CLKO_Enable(); //Êä³öʱÖÓ + else Timer4_CLKO_Disable(); //²»Êä³öʱÖÓ + + T4_Load(TIMx->TIM_Value); + if(TIMx->TIM_Run == ENABLE) Timer4_Run(); //¿ªÊ¼ÔËÐÐ + return 0; //³É¹¦ + } + return 2; //´íÎó +} +/************************ ?¡§?¡À?¡Â???? ****************************/ +void Timer_config(void) +{ + TIM_InitTypeDef TIM_InitStructure; + TIM_InitStructure.TIM_Mode = TIM_16BitAutoReload; + TIM_InitStructure.TIM_Priority = Priority_0; + TIM_InitStructure.TIM_Interrupt = ENABLE; + TIM_InitStructure.TIM_ClkSource = TIM_CLOCK_1T; + TIM_InitStructure.TIM_ClkOut = DISABLE; + TIM_InitStructure.TIM_Value = 65536UL - (MAIN_Fosc / 1000UL); + TIM_InitStructure.TIM_Run = ENABLE; + Timer_Inilize(Timer0,&TIM_InitStructure); +} \ No newline at end of file diff --git a/myinc/Exti.h b/myinc/Exti.h new file mode 100644 index 0000000..d660b79 --- /dev/null +++ b/myinc/Exti.h @@ -0,0 +1,38 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* ���Ҫ�ڳ�����ʹ�ô˴���,���ڳ�����ע��ʹ����STC�����ϼ����� */ +/*---------------------------------------------------------------------*/ + +#ifndef __EXTI_H +#define __EXTI_H + +#include "config.h" +#include "GPIO.h" +#include "timer.h" + +#define EXT_INT0 0 // ��ʼ�����ж�0 +#define EXT_INT1 1 // ��ʼ�����ж�1 +#define EXT_INT2 2 // ��ʼ�����ж�2 +#define EXT_INT3 3 // ��ʼ�����ж�3 +#define EXT_INT4 4 // ��ʼ�����ж�4 + +#define EXT_MODE_RiseFall 0 // ������/�½����ж� +#define EXT_MODE_Fall 1 // �½����ж� + +typedef struct +{ + u8 EXTI_Mode; // �ж�ģʽ, EXT_MODE_RiseFall, EXT_MODE_Fall + u8 EXTI_Priority; // ���ȼ����� Priority_0,Priority_1,Priority_2,Priority_3 + u8 EXTI_Interrupt; // ����� ENABLE,DISABLE +} EXTI_InitTypeDef; + +u8 Ext_Inilize(u8 EXT, EXTI_InitTypeDef *INTx); +void Exti_config(void); +#endif diff --git a/myinc/GPIO.h b/myinc/GPIO.h new file mode 100644 index 0000000..f1d9c72 --- /dev/null +++ b/myinc/GPIO.h @@ -0,0 +1,53 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ +/*---------------------------------------------------------------------*/ + +#ifndef __GPIO_H +#define __GPIO_H + +#include "config.h" + +#define GPIO_PullUp 0 //ÉÏÀ­×¼Ë«Ïò¿Ú +#define GPIO_HighZ 1 //¸¡¿ÕÊäÈë +#define GPIO_OUT_OD 2 //¿ªÂ©Êä³ö +#define GPIO_OUT_PP 3 //ÍÆÍìÊä³ö + +#define GPIO_Pin_0 0x01 //IOÒý½Å Px.0 +#define GPIO_Pin_1 0x02 //IOÒý½Å Px.1 +#define GPIO_Pin_2 0x04 //IOÒý½Å Px.2 +#define GPIO_Pin_3 0x08 //IOÒý½Å Px.3 +#define GPIO_Pin_4 0x10 //IOÒý½Å Px.4 +#define GPIO_Pin_5 0x20 //IOÒý½Å Px.5 +#define GPIO_Pin_6 0x40 //IOÒý½Å Px.6 +#define GPIO_Pin_7 0x80 //IOÒý½Å Px.7 +#define GPIO_Pin_All 0xFF //IOËùÓÐÒý½Å + +#define GPIO_P0 0 // +#define GPIO_P1 1 +#define GPIO_P2 2 +#define GPIO_P3 3 +#define GPIO_P4 4 +#define GPIO_P5 5 +#define GPIO_P6 6 +#define GPIO_P7 7 +#define kill_gpio P32 +#define power1_gpio P10 +#define power2_gpio P11 +#define power3_gpio P12 +typedef struct +{ + u8 Mode; //IOģʽ, GPIO_PullUp,GPIO_HighZ,GPIO_OUT_OD,GPIO_OUT_PP + u8 Pin; //ÒªÉèÖÃµÄ¶Ë¿Ú +} GPIO_InitTypeDef; + +u8 GPIO_Inilize(u8 GPIO, GPIO_InitTypeDef *GPIOx); +void GPIO_config(void); +#endif diff --git a/myinc/STC8xxxx.H b/myinc/STC8xxxx.H new file mode 100644 index 0000000..18458c7 --- /dev/null +++ b/myinc/STC8xxxx.H @@ -0,0 +1,2747 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* Èç¹ûÒªÔÚ³ÌÐòÖÐʹÓô˴úÂë,ÇëÔÚ³ÌÐòÖÐ×¢Ã÷ʹÓÃÁËSTCµÄ×ÊÁϼ°³ÌÐò */ +/*---------------------------------------------------------------------*/ + +#ifndef _STC8xxxx_H +#define _STC8xxxx_H + +#include + +/* BYTE Registers */ +sfr P0 = 0x80; +sfr SP = 0x81; +sfr DPL = 0x82; +sfr DPH = 0x83; +sfr S4CON = 0x84; +sfr S4BUF = 0x85; +sfr PCON = 0x87; + +sfr TCON = 0x88; +sfr TMOD = 0x89; +sfr TL0 = 0x8A; +sfr TL1 = 0x8B; +sfr TH0 = 0x8C; +sfr TH1 = 0x8D; +sfr AUXR = 0x8E; +sfr WAKE_CLKO = 0x8F; +sfr INT_CLKO = 0x8F; + +sfr P1 = 0x90; +sfr P1M1 = 0x91; //P1M1.n,P1M0.n =00--->Standard, 01--->push-pull ʵ¼ÊÉÏ1TµÄ¶¼Ò»Ñù +sfr P1M0 = 0x92; // =10--->pure input, 11--->open drain +sfr P0M1 = 0x93; //P0M1.n,P0M0.n =00--->Standard, 01--->push-pull +sfr P0M0 = 0x94; // =10--->pure input, 11--->open drain +sfr P2M1 = 0x95; //P2M1.n,P2M0.n =00--->Standard, 01--->push-pull +sfr P2M0 = 0x96; // =10--->pure input, 11--->open drain +//sfr PCON2 = 0x97; +//sfr AUXR2 = 0x97; + +sfr SCON = 0x98; +sfr SBUF = 0x99; +sfr S2CON = 0x9A; // +sfr S2BUF = 0x9B; // + +sfr P2 = 0xA0; +sfr BUS_SPEED = 0xA1; +sfr P_SW1 = 0xA2; + +sfr IE = 0xA8; +sfr SADDR = 0xA9; +sfr WKTCL = 0xAA; //»½ÐѶ¨Ê±Æ÷µÍ×Ö½Ú +sfr WKTCH = 0xAB; //»½ÐѶ¨Ê±Æ÷¸ß×Ö½Ú +sfr S3CON = 0xAC; +sfr S3BUF = 0xAD; +sfr TA = 0xAE; +sfr IE2 = 0xAF; + +sfr P3 = 0xB0; +sfr P3M1 = 0xB1; //P3M1.n,P3M0.n =00--->Standard, 01--->push-pull +sfr P3M0 = 0xB2; // =10--->pure input, 11--->open drain +sfr P4M1 = 0xB3; //P4M1.n,P4M0.n =00--->Standard, 01--->push-pull +sfr P4M0 = 0xB4; // =10--->pure input, 11--->open drain +sfr IP2 = 0xB5; +sfr IP2H = 0xB6; +sfr IPH = 0xB7; + +sfr IP = 0xB8; +sfr SADEN = 0xB9; +sfr P_SW2 = 0xBA; +sfr VOCTRL = 0xBB; +sfr ADC_CONTR = 0xBC; //ADC¿ØÖƼĴæÆ÷ +sfr ADC_RES = 0xBD; //ADC½á¹û¸ß×Ö½Ú +sfr ADC_RESL = 0xBE; //ADC½á¹ûµÍ×Ö½Ú + +sfr P4 = 0xC0; +sfr WDT_CONTR = 0xC1; + +sfr IAP_DATA = 0xC2; +sfr IAP_ADDRH = 0xC3; +sfr IAP_ADDRL = 0xC4; +sfr IAP_CMD = 0xC5; +sfr IAP_TRIG = 0xC6; +sfr IAP_CONTR = 0xC7; + +sfr ISP_DATA = 0xC2; +sfr ISP_ADDRH = 0xC3; +sfr ISP_ADDRL = 0xC4; +sfr ISP_CMD = 0xC5; +sfr ISP_TRIG = 0xC6; +sfr ISP_CONTR = 0xC7; + +sfr P5 = 0xC8; // +sfr P5M1 = 0xC9; // P5M1.n,P5M0.n =00--->Standard, 01--->push-pull +sfr P5M0 = 0xCA; // =10--->pure input, 11--->open drain +sfr P6M1 = 0xCB; // P5M1.n,P5M0.n =00--->Standard, 01--->push-pull +sfr P6M0 = 0xCC; // =10--->pure input, 11--->open drain +sfr SPSTAT = 0xCD; // +sfr SPCTL = 0xCE; // +sfr SPDAT = 0xCF; // + +sfr PSW = 0xD0; +sfr T4T3M = 0xD1; +sfr T4H = 0xD2; +sfr T4L = 0xD3; +sfr T3H = 0xD4; +sfr T3L = 0xD5; +sfr T2H = 0xD6; +sfr T2L = 0xD7; + +sfr TH4 = 0xD2; +sfr TL4 = 0xD3; +sfr TH3 = 0xD4; +sfr TL3 = 0xD5; +sfr TH2 = 0xD6; +sfr TL2 = 0xD7; + +sfr CCON = 0xD8; // +sfr CMOD = 0xD9; // +sfr CCAPM0 = 0xDA; //PCAÄ£¿é0µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£ +sfr CCAPM1 = 0xDB; //PCAÄ£¿é1µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£ +sfr CCAPM2 = 0xDC; //PCAÄ£¿é2µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£ +//sfr CCAPM3 = 0xDD; //PCAÄ£¿é3µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£ +sfr USBCLK = 0xDC; +sfr ADCCFG = 0xDE; // +sfr IP3 = 0xDF; //ÖжÏÓÅÏȼ¶¼Ä´æÆ÷ + +sfr ACC = 0xE0; +sfr P7M1 = 0xE1; +sfr P7M0 = 0xE2; +sfr DPS = 0xE3; +sfr DPL1 = 0xE4; +sfr DPH1 = 0xE5; +sfr CMPCR1 = 0xE6; +sfr CMPCR2 = 0xE7; + +sfr P6 = 0xE8; +sfr CL = 0xE9; // +sfr CCAP0L = 0xEA; //PCAÄ£¿é0µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£ +sfr CCAP1L = 0xEB; //PCAÄ£¿é1µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£ +sfr CCAP2L = 0xEC; //PCAÄ£¿é2µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£ +//sfr CCAP3L = 0xED; //PCAÄ£¿é3µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£ +sfr USBDAT = 0xEC; +sfr IP3H = 0xEE; +sfr AUXINTIF = 0xEF; //¸¨ÖúÖжϱêÖ¾ B6-INT4IF, B5-INT3IF, B4-INT2IF, B2-T4IF, B1-T3IF, B0-T2IF + +sfr B = 0xF0; +sfr PWMSET = 0xF1; //ÔöÇ¿ÐÍPWMÈ«¾ÖÅäÖüĴæÆ÷ +sfr PCA_PWM0 = 0xF2; //PCAÄ£¿é0 PWM¼Ä´æÆ÷¡£ +sfr PCA_PWM1 = 0xF3; //PCAÄ£¿é1 PWM¼Ä´æÆ÷¡£ +sfr PCA_PWM2 = 0xF4; //PCAÄ£¿é2 PWM¼Ä´æÆ÷¡£ +//sfr PCA_PWM3 = 0xF5; //PCAÄ£¿é3 PWM¼Ä´æÆ÷¡£ +sfr PWMCFG01 = 0xF6; //ÔöÇ¿ÐÍPWMÅäÖüĴæÆ÷ +sfr PWMCFG23 = 0xF7; //ÔöÇ¿ÐÍPWMÅäÖüĴæÆ÷ +sfr USBCON = 0xF4; +sfr IAP_TPS = 0xF5; + +sfr P7 = 0xF8; +sfr CH = 0xF9; +sfr CCAP0H = 0xFA; //PCAÄ£¿é0µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£ +sfr CCAP1H = 0xFB; //PCAÄ£¿é1µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£ +sfr CCAP2H = 0xFC; //PCAÄ£¿é2µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£ +//sfr CCAP3H = 0xFD; //PCAÄ£¿é3µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£ +sfr PWMCFG45 = 0xFE; //ÔöÇ¿ÐÍPWMÅäÖüĴæÆ÷ +sfr USBADR = 0xFC; +sfr RSTCFG = 0xFF; // + + +// 7 6 5 4 3 2 1 0 Reset Value +//INT_CLKO: ÖжÏÓëʱÖÓÊä³ö¿ØÖƼĴæÆ÷ - EX4 EX3 EX2 - T2CLKO T1CLKO T0CLKO 0000,0000 +#define INT4_Enable() INT_CLKO |= (1 << 6) +#define INT3_Enable() INT_CLKO |= (1 << 5) +#define INT2_Enable() INT_CLKO |= (1 << 4) +#define INT1_Enable() EX1 = 1 +#define INT0_Enable() EX0 = 1 + +#define INT4_Disable() INT_CLKO &= ~(1 << 6) +#define INT3_Disable() INT_CLKO &= ~(1 << 5) +#define INT2_Disable() INT_CLKO &= ~(1 << 4) +#define INT1_Disable() EX1 = 0 +#define INT0_Disable() EX0 = 0 + +// 7 6 5 4 3 2 1 0 Reset Value +//AUXINTIF: ¸¨ÖúÖжϱêÖ¾¼Ä´æÆ÷ - INT4IF INT3IF INT2IF - T4IF T3IF T2IF 0000,0000 +#define INT4IF 0x40 +#define INT3IF 0x20 +#define INT2IF 0x10 +#define T4IF 0x04 +#define T3IF 0x02 +#define T2IF 0x01 + +#define INT4_Clear() AUXINTIF &= ~INT4IF /* Çå³ýÍâÖжÏ4±ê־λ */ +#define INT3_Clear() AUXINTIF &= ~INT3IF /* Çå³ýÍâÖжÏ3±ê־λ */ +#define INT2_Clear() AUXINTIF &= ~INT2IF /* Çå³ýÍâÖжÏ2±ê־λ */ +#define INT1_Clear() IE1 = 0 /* Çå³ýÍâÖжÏ1±ê־λ */ +#define INT0_Clear() IE0 = 0 /* Çå³ýÍâÖжÏ0±ê־λ */ + +#define INT0_Fall() IT0 = 1 /* INT0 ϽµÑØÖÐ¶Ï */ +#define INT0_RiseFall() IT0 = 0 /* INT0 ϽµÑØÉÏÉýÑؾùÖÐ¶Ï */ +#define INT1_Fall() IT1 = 1 /* INT1 ϽµÑØÖÐ¶Ï */ +#define INT1_RiseFall() IT0 = 0 /* INT1 ϽµÑØÉÏÉýÑؾùÖÐ¶Ï */ + + +//=============================================================== +#define EAXSFR() P_SW2 |= 0x80 /* MOVX A,@DPTR/MOVX @DPTR,AÖ¸ÁîµÄ²Ù×÷¶ÔÏóΪÀ©Õ¹SFR(XSFR) */ +#define EAXRAM() P_SW2 &= ~0x80 /* MOVX A,@DPTR/MOVX @DPTR,AÖ¸ÁîµÄ²Ù×÷¶ÔÏóΪÀ©Õ¹RAM(XRAM) */ + +#define I2C_USE_P14P15() P_SW2 &= ~0x30 /* ½«I2CÇл»µ½P1.4(SDA) P1.5(SCL)(ÉϵçĬÈÏ).*/ +#define I2C_USE_P24P25() P_SW2 = (P_SW2 & ~0x30) | 0x10 /* ½«I2CÇл»µ½P2.4(SDA) P2.5(SCL).*/ +#define I2C_USE_P76P77() P_SW2 = (P_SW2 & ~0x30) | 0x20 /* ½«I2CÇл»µ½P7.6(SDA) P7.7(SCL).*/ +#define I2C_USE_P33P32() P_SW2 |= 0x30 /* ½«I2CÇл»µ½P3.3(SDA) P3.2(SCL).*/ + +#define CLKSEL (*(unsigned char volatile xdata *)0xfe00) +#define CKSEL (*(unsigned char volatile xdata *)0xfe00) /* Ö÷ʱÖÓÔ´Ñ¡Ôñ */ +#define CLKDIV (*(unsigned char volatile xdata *)0xfe01) /* Ö÷ʱÖÓ·ÖƵ */ +#define IRC24MCR (*(unsigned char volatile xdata *)0xfe02) /* IRC 24MHZ¿ØÖÆ */ +#define XOSCCR (*(unsigned char volatile xdata *)0xfe03) /* XOSC¿ØÖÆ */ +#define IRC32KCR (*(unsigned char volatile xdata *)0xfe04) /* IRC 32KHZ¿ØÖÆ */ +#define MCLKOCR (*(unsigned char volatile xdata *)0xfe05) +#define IRCDB (*(unsigned char volatile xdata *)0xfe06) +#define X32KCR (*(unsigned char volatile xdata *)0xfe08) + +#define MainFosc_IRC24M() CKSEL = (CKSEL & ~0x03) /* Ñ¡ÔñÄÚ²¿24MHZʱÖÓ */ +#define MainFosc_XTAL() CKSEL = (CKSEL & ~0x03) | 0x01 /* Ñ¡ÔñÍⲿ¾§Õñ»òʱÖÓ */ +#define MainFosc_IRC32K() CKSEL = CKSEL | 0x03 /* Ñ¡ÔñÄÚ²¿32KʱÖÓ */ +#define EXT_CLOCK() XOSCCR = 0x80 /* Ñ¡ÔñÍⲿʱÖÓ */ +#define EXT_CRYSTAL() XOSCCR = 0xC0 /* Ñ¡ÔñÍⲿ¾§Õñ */ + + +#define P0PU (*(unsigned char volatile xdata *)0xfe10) /* P0 4.1K Pull Up Enable */ +#define P1PU (*(unsigned char volatile xdata *)0xfe11) /* P1 4.1K Pull Up Enable */ +#define P2PU (*(unsigned char volatile xdata *)0xfe12) /* P2 4.1K Pull Up Enable */ +#define P3PU (*(unsigned char volatile xdata *)0xfe13) /* P3 4.1K Pull Up Enable */ +#define P4PU (*(unsigned char volatile xdata *)0xfe14) /* P4 4.1K Pull Up Enable */ +#define P5PU (*(unsigned char volatile xdata *)0xfe15) /* P5 4.1K Pull Up Enable */ +#define P6PU (*(unsigned char volatile xdata *)0xfe16) /* P6 4.1K Pull Up Enable */ +#define P7PU (*(unsigned char volatile xdata *)0xfe17) /* P7 4.1K Pull Up Enable */ + +#define P0NCS (*(unsigned char volatile xdata *)0xfe18) /* P0 Non Schmit Trigger 0: ʹÄܶ˿ÚÊ©ÃÜÌØ´¥·¢¹¦ÄÜ(ĬÈÏ), 1: ½ûÖ¹ */ +#define P1NCS (*(unsigned char volatile xdata *)0xfe19) /* P1 Non Schmit Trigger */ +#define P2NCS (*(unsigned char volatile xdata *)0xfe1a) /* P2 Non Schmit Trigger */ +#define P3NCS (*(unsigned char volatile xdata *)0xfe1b) /* P3 Non Schmit Trigger */ +#define P4NCS (*(unsigned char volatile xdata *)0xfe1c) /* P4 Non Schmit Trigger */ +#define P5NCS (*(unsigned char volatile xdata *)0xfe1d) /* P5 Non Schmit Trigger */ +#define P6NCS (*(unsigned char volatile xdata *)0xfe1e) /* P6 Non Schmit Trigger */ +#define P7NCS (*(unsigned char volatile xdata *)0xfe1f) /* P7 Non Schmit Trigger */ + +#define P0SR (*(unsigned char volatile xdata *)0xfe20) /* ¶Ë¿Úµçƽת»»ËÙ¶È 0: ¿ì, 1: Âý(ĬÈÏ) */ +#define P1SR (*(unsigned char volatile xdata *)0xfe21) +#define P2SR (*(unsigned char volatile xdata *)0xfe22) +#define P3SR (*(unsigned char volatile xdata *)0xfe23) +#define P4SR (*(unsigned char volatile xdata *)0xfe24) +#define P5SR (*(unsigned char volatile xdata *)0xfe25) +#define P6SR (*(unsigned char volatile xdata *)0xfe26) +#define P7SR (*(unsigned char volatile xdata *)0xfe27) + +#define P0DR (*(unsigned char volatile xdata *)0xfe28) /* ¶Ë¿ÚÇý¶¯µçÁ÷¿ØÖÆ 0: ÔöÇ¿Çý¶¯ÄÜÁ¦, 1: Ò»°ãÇý¶¯ÄÜÁ¦(ĬÈÏ) */ +#define P1DR (*(unsigned char volatile xdata *)0xfe29) +#define P2DR (*(unsigned char volatile xdata *)0xfe2a) +#define P3DR (*(unsigned char volatile xdata *)0xfe2b) +#define P4DR (*(unsigned char volatile xdata *)0xfe2c) +#define P5DR (*(unsigned char volatile xdata *)0xfe2d) +#define P6DR (*(unsigned char volatile xdata *)0xfe2e) +#define P7DR (*(unsigned char volatile xdata *)0xfe2f) + +#define P0IE (*(unsigned char volatile xdata *)0xfe30)/* ¶Ë¿ÚÊý×ÖÐźÅÊäÈëʹÄÜ 0: ½ûÖ¹Êý×ÖÐźÅÊäÈë, 1: ʹÄÜÊý×ÖÐźÅÊäÈë(ĬÈÏ) */ +#define P1IE (*(unsigned char volatile xdata *)0xfe31) +#define P2IE (*(unsigned char volatile xdata *)0xfe32) +#define P3IE (*(unsigned char volatile xdata *)0xfe33) +#define P4IE (*(unsigned char volatile xdata *)0xfe34) +#define P5IE (*(unsigned char volatile xdata *)0xfe35) +#define P6IE (*(unsigned char volatile xdata *)0xfe36) +#define P7IE (*(unsigned char volatile xdata *)0xfe37) + +#define I2CCFG (*(unsigned char volatile xdata *)0xfe80) /* */ +#define I2CMSCR (*(unsigned char volatile xdata *)0xfe81) /* */ +#define I2CMSST (*(unsigned char volatile xdata *)0xfe82) /* */ +#define I2CSLCR (*(unsigned char volatile xdata *)0xfe83) /* */ +#define I2CSLST (*(unsigned char volatile xdata *)0xfe84) /* */ +#define I2CSLADR (*(unsigned char volatile xdata *)0xfe85) /* */ +#define I2CTXD (*(unsigned char volatile xdata *)0xfe86) /* */ +#define I2CRXD (*(unsigned char volatile xdata *)0xfe87) /* */ +#define I2CMSAUX (*(unsigned char volatile xdata *)0xfe88) + +#define TM2PS (*(unsigned char volatile xdata *)0xfea2) +#define TM3PS (*(unsigned char volatile xdata *)0xfea3) +#define TM4PS (*(unsigned char volatile xdata *)0xfea4) +#define ADCTIM (*(unsigned char volatile xdata *)0xfea8) +#define T3T4PIN (*(unsigned char volatile xdata *)0xfeac) + +#define PWMA_ETRPS (*(unsigned char volatile xdata *)0xfeb0) +#define PWMA_ENO (*(unsigned char volatile xdata *)0xfeb1) +#define PWMA_PS (*(unsigned char volatile xdata *)0xfeb2) +#define PWMA_IOAUX (*(unsigned char volatile xdata *)0xfeb3) +#define PWMB_ETRPS (*(unsigned char volatile xdata *)0xfeb4) +#define PWMB_ENO (*(unsigned char volatile xdata *)0xfeb5) +#define PWMB_PS (*(unsigned char volatile xdata *)0xfeb6) +#define PWMB_IOAUX (*(unsigned char volatile xdata *)0xfeb7) +#define PWMA_CR1 (*(unsigned char volatile xdata *)0xfec0) +#define PWMA_CR2 (*(unsigned char volatile xdata *)0xfec1) +#define PWMA_SMCR (*(unsigned char volatile xdata *)0xfec2) +#define PWMA_ETR (*(unsigned char volatile xdata *)0xfec3) +#define PWMA_IER (*(unsigned char volatile xdata *)0xfec4) +#define PWMA_SR1 (*(unsigned char volatile xdata *)0xfec5) +#define PWMA_SR2 (*(unsigned char volatile xdata *)0xfec6) +#define PWMA_EGR (*(unsigned char volatile xdata *)0xfec7) +#define PWMA_CCMR1 (*(unsigned char volatile xdata *)0xfec8) +#define PWMA_CCMR2 (*(unsigned char volatile xdata *)0xfec9) +#define PWMA_CCMR3 (*(unsigned char volatile xdata *)0xfeca) +#define PWMA_CCMR4 (*(unsigned char volatile xdata *)0xfecb) +#define PWMA_CCER1 (*(unsigned char volatile xdata *)0xfecc) +#define PWMA_CCER2 (*(unsigned char volatile xdata *)0xfecd) +#define PWMA_CNTR (*(unsigned int volatile xdata *)0xfece) +#define PWMA_CNTRH (*(unsigned char volatile xdata *)0xfece) +#define PWMA_CNTRL (*(unsigned char volatile xdata *)0xfecf) +#define PWMA_PSCR (*(unsigned int volatile xdata *)0xfed0) +#define PWMA_PSCRH (*(unsigned char volatile xdata *)0xfed0) +#define PWMA_PSCRL (*(unsigned char volatile xdata *)0xfed1) +#define PWMA_ARR (*(unsigned int volatile xdata *)0xfed2) +#define PWMA_ARRH (*(unsigned char volatile xdata *)0xfed2) +#define PWMA_ARRL (*(unsigned char volatile xdata *)0xfed3) +#define PWMA_RCR (*(unsigned char volatile xdata *)0xfed4) +#define PWMA_CCR1 (*(unsigned int volatile xdata *)0xfed5) +#define PWMA_CCR1H (*(unsigned char volatile xdata *)0xfed5) +#define PWMA_CCR1L (*(unsigned char volatile xdata *)0xfed6) +#define PWMA_CCR2 (*(unsigned int volatile xdata *)0xfed7) +#define PWMA_CCR2H (*(unsigned char volatile xdata *)0xfed7) +#define PWMA_CCR2L (*(unsigned char volatile xdata *)0xfed8) +#define PWMA_CCR3 (*(unsigned int volatile xdata *)0xfed9) +#define PWMA_CCR3H (*(unsigned char volatile xdata *)0xfed9) +#define PWMA_CCR3L (*(unsigned char volatile xdata *)0xfeda) +#define PWMA_CCR4 (*(unsigned int volatile xdata *)0xfedb) +#define PWMA_CCR4H (*(unsigned char volatile xdata *)0xfedb) +#define PWMA_CCR4L (*(unsigned char volatile xdata *)0xfedc) +#define PWMA_BRK (*(unsigned char volatile xdata *)0xfedd) +#define PWMA_DTR (*(unsigned char volatile xdata *)0xfede) +#define PWMA_OISR (*(unsigned char volatile xdata *)0xfedf) + +#define PWMB_CR1 (*(unsigned char volatile xdata *)0xfee0) +#define PWMB_CR2 (*(unsigned char volatile xdata *)0xfee1) +#define PWMB_SMCR (*(unsigned char volatile xdata *)0xfee2) +#define PWMB_ETR (*(unsigned char volatile xdata *)0xfee3) +#define PWMB_IER (*(unsigned char volatile xdata *)0xfee4) +#define PWMB_SR1 (*(unsigned char volatile xdata *)0xfee5) +#define PWMB_SR2 (*(unsigned char volatile xdata *)0xfee6) +#define PWMB_EGR (*(unsigned char volatile xdata *)0xfee7) +#define PWMB_CCMR1 (*(unsigned char volatile xdata *)0xfee8) +#define PWMB_CCMR2 (*(unsigned char volatile xdata *)0xfee9) +#define PWMB_CCMR3 (*(unsigned char volatile xdata *)0xfeea) +#define PWMB_CCMR4 (*(unsigned char volatile xdata *)0xfeeb) +#define PWMB_CCER1 (*(unsigned char volatile xdata *)0xfeec) +#define PWMB_CCER2 (*(unsigned char volatile xdata *)0xfeed) +#define PWMB_CNTR (*(unsigned int volatile xdata *)0xfeee) +#define PWMB_CNTRH (*(unsigned char volatile xdata *)0xfeee) +#define PWMB_CNTRL (*(unsigned char volatile xdata *)0xfeef) +#define PWMB_PSCR (*(unsigned int volatile xdata *)0xfef0) +#define PWMB_PSCRH (*(unsigned char volatile xdata *)0xfef0) +#define PWMB_PSCRL (*(unsigned char volatile xdata *)0xfef1) +#define PWMB_ARR (*(unsigned int volatile xdata *)0xfef2) +#define PWMB_ARRH (*(unsigned char volatile xdata *)0xfef2) +#define PWMB_ARRL (*(unsigned char volatile xdata *)0xfef3) +#define PWMB_RCR (*(unsigned char volatile xdata *)0xfef4) +#define PWMB_CCR5 (*(unsigned int volatile xdata *)0xfef5) +#define PWMB_CCR5H (*(unsigned char volatile xdata *)0xfef5) +#define PWMB_CCR5L (*(unsigned char volatile xdata *)0xfef6) +#define PWMB_CCR6 (*(unsigned int volatile xdata *)0xfef7) +#define PWMB_CCR6H (*(unsigned char volatile xdata *)0xfef7) +#define PWMB_CCR6L (*(unsigned char volatile xdata *)0xfef8) +#define PWMB_CCR7 (*(unsigned int volatile xdata *)0xfef9) +#define PWMB_CCR7H (*(unsigned char volatile xdata *)0xfef9) +#define PWMB_CCR7L (*(unsigned char volatile xdata *)0xfefa) +#define PWMB_CCR8 (*(unsigned int volatile xdata *)0xfefb) +#define PWMB_CCR8H (*(unsigned char volatile xdata *)0xfefb) +#define PWMB_CCR8L (*(unsigned char volatile xdata *)0xfefc) +#define PWMB_BRK (*(unsigned char volatile xdata *)0xfefd) +#define PWMB_DTR (*(unsigned char volatile xdata *)0xfefe) +#define PWMB_OISR (*(unsigned char volatile xdata *)0xfeff) + +///////////////////////////////////////////////// +//FD00H-FDFFH +///////////////////////////////////////////////// + +#define PWM0C (*(unsigned int volatile xdata *)0xff00) +#define PWM0CH (*(unsigned char volatile xdata *)0xff00) +#define PWM0CL (*(unsigned char volatile xdata *)0xff01) +#define PWM0CKS (*(unsigned char volatile xdata *)0xff02) +#define PWM0TADC (*(unsigned int volatile xdata *)0xff03) +#define PWM0TADCH (*(unsigned char volatile xdata *)0xff03) +#define PWM0TADCL (*(unsigned char volatile xdata *)0xff04) +#define PWM0IF (*(unsigned char volatile xdata *)0xff05) +#define PWM0FDCR (*(unsigned char volatile xdata *)0xff06) +#define PWM00T1 (*(unsigned int volatile xdata *)0xff10) +#define PWM00T1H (*(unsigned char volatile xdata *)0xff10) +#define PWM00T1L (*(unsigned char volatile xdata *)0xff11) +#define PWM00T2 (*(unsigned int volatile xdata *)0xff12) +#define PWM00T2H (*(unsigned char volatile xdata *)0xff12) +#define PWM00T2L (*(unsigned char volatile xdata *)0xff13) +#define PWM00CR (*(unsigned char volatile xdata *)0xff14) +#define PWM00HLD (*(unsigned char volatile xdata *)0xff15) +#define PWM01T1 (*(unsigned int volatile xdata *)0xff18) +#define PWM01T1H (*(unsigned char volatile xdata *)0xff18) +#define PWM01T1L (*(unsigned char volatile xdata *)0xff19) +#define PWM01T2 (*(unsigned int volatile xdata *)0xff1a) +#define PWM01T2H (*(unsigned char volatile xdata *)0xff1a) +#define PWM01T2L (*(unsigned char volatile xdata *)0xff1b) +#define PWM01CR (*(unsigned char volatile xdata *)0xff1c) +#define PWM01HLD (*(unsigned char volatile xdata *)0xff1d) +#define PWM02T1 (*(unsigned int volatile xdata *)0xff20) +#define PWM02T1H (*(unsigned char volatile xdata *)0xff20) +#define PWM02T1L (*(unsigned char volatile xdata *)0xff21) +#define PWM02T2 (*(unsigned int volatile xdata *)0xff22) +#define PWM02T2H (*(unsigned char volatile xdata *)0xff22) +#define PWM02T2L (*(unsigned char volatile xdata *)0xff23) +#define PWM02CR (*(unsigned char volatile xdata *)0xff24) +#define PWM02HLD (*(unsigned char volatile xdata *)0xff25) +#define PWM03T1 (*(unsigned int volatile xdata *)0xff28) +#define PWM03T1H (*(unsigned char volatile xdata *)0xff28) +#define PWM03T1L (*(unsigned char volatile xdata *)0xff29) +#define PWM03T2 (*(unsigned int volatile xdata *)0xff2a) +#define PWM03T2H (*(unsigned char volatile xdata *)0xff2a) +#define PWM03T2L (*(unsigned char volatile xdata *)0xff2b) +#define PWM03CR (*(unsigned char volatile xdata *)0xff2c) +#define PWM03HLD (*(unsigned char volatile xdata *)0xff2d) +#define PWM04T1 (*(unsigned int volatile xdata *)0xff30) +#define PWM04T1H (*(unsigned char volatile xdata *)0xff30) +#define PWM04T1L (*(unsigned char volatile xdata *)0xff31) +#define PWM04T2 (*(unsigned int volatile xdata *)0xff32) +#define PWM04T2H (*(unsigned char volatile xdata *)0xff32) +#define PWM04T2L (*(unsigned char volatile xdata *)0xff33) +#define PWM04CR (*(unsigned char volatile xdata *)0xff34) +#define PWM04HLD (*(unsigned char volatile xdata *)0xff35) +#define PWM05T1 (*(unsigned int volatile xdata *)0xff38) +#define PWM05T1H (*(unsigned char volatile xdata *)0xff38) +#define PWM05T1L (*(unsigned char volatile xdata *)0xff39) +#define PWM05T2 (*(unsigned int volatile xdata *)0xff3a) +#define PWM05T2H (*(unsigned char volatile xdata *)0xff3a) +#define PWM05T2L (*(unsigned char volatile xdata *)0xff3b) +#define PWM05CR (*(unsigned char volatile xdata *)0xff3c) +#define PWM05HLD (*(unsigned char volatile xdata *)0xff3d) +#define PWM06T1 (*(unsigned int volatile xdata *)0xff40) +#define PWM06T1H (*(unsigned char volatile xdata *)0xff40) +#define PWM06T1L (*(unsigned char volatile xdata *)0xff41) +#define PWM06T2 (*(unsigned int volatile xdata *)0xff42) +#define PWM06T2H (*(unsigned char volatile xdata *)0xff42) +#define PWM06T2L (*(unsigned char volatile xdata *)0xff43) +#define PWM06CR (*(unsigned char volatile xdata *)0xff44) +#define PWM06HLD (*(unsigned char volatile xdata *)0xff45) +#define PWM07T1 (*(unsigned int volatile xdata *)0xff48) +#define PWM07T1H (*(unsigned char volatile xdata *)0xff48) +#define PWM07T1L (*(unsigned char volatile xdata *)0xff49) +#define PWM07T2 (*(unsigned int volatile xdata *)0xff4a) +#define PWM07T2H (*(unsigned char volatile xdata *)0xff4a) +#define PWM07T2L (*(unsigned char volatile xdata *)0xff4b) +#define PWM07CR (*(unsigned char volatile xdata *)0xff4c) +#define PWM07HLD (*(unsigned char volatile xdata *)0xff4d) +#define PWM1C (*(unsigned int volatile xdata *)0xff50) +#define PWM1CH (*(unsigned char volatile xdata *)0xff50) +#define PWM1CL (*(unsigned char volatile xdata *)0xff51) +#define PWM1CKS (*(unsigned char volatile xdata *)0xff52) +#define PWM1IF (*(unsigned char volatile xdata *)0xff55) +#define PWM1FDCR (*(unsigned char volatile xdata *)0xff56) +#define PWM10T1 (*(unsigned int volatile xdata *)0xff60) +#define PWM10T1H (*(unsigned char volatile xdata *)0xff60) +#define PWM10T1L (*(unsigned char volatile xdata *)0xff61) +#define PWM10T2 (*(unsigned int volatile xdata *)0xff62) +#define PWM10T2H (*(unsigned char volatile xdata *)0xff62) +#define PWM10T2L (*(unsigned char volatile xdata *)0xff63) +#define PWM10CR (*(unsigned char volatile xdata *)0xff64) +#define PWM10HLD (*(unsigned char volatile xdata *)0xff65) +#define PWM11T1 (*(unsigned int volatile xdata *)0xff68) +#define PWM11T1H (*(unsigned char volatile xdata *)0xff68) +#define PWM11T1L (*(unsigned char volatile xdata *)0xff69) +#define PWM11T2 (*(unsigned int volatile xdata *)0xff6a) +#define PWM11T2H (*(unsigned char volatile xdata *)0xff6a) +#define PWM11T2L (*(unsigned char volatile xdata *)0xff6b) +#define PWM11CR (*(unsigned char volatile xdata *)0xff6c) +#define PWM11HLD (*(unsigned char volatile xdata *)0xff6d) +#define PWM12T1 (*(unsigned int volatile xdata *)0xff70) +#define PWM12T1H (*(unsigned char volatile xdata *)0xff70) +#define PWM12T1L (*(unsigned char volatile xdata *)0xff71) +#define PWM12T2 (*(unsigned int volatile xdata *)0xff72) +#define PWM12T2H (*(unsigned char volatile xdata *)0xff72) +#define PWM12T2L (*(unsigned char volatile xdata *)0xff73) +#define PWM12CR (*(unsigned char volatile xdata *)0xff74) +#define PWM12HLD (*(unsigned char volatile xdata *)0xff75) +#define PWM13T1 (*(unsigned int volatile xdata *)0xff78) +#define PWM13T1H (*(unsigned char volatile xdata *)0xff78) +#define PWM13T1L (*(unsigned char volatile xdata *)0xff79) +#define PWM13T2 (*(unsigned int volatile xdata *)0xff7a) +#define PWM13T2H (*(unsigned char volatile xdata *)0xff7a) +#define PWM13T2L (*(unsigned char volatile xdata *)0xff7b) +#define PWM13CR (*(unsigned char volatile xdata *)0xff7c) +#define PWM13HLD (*(unsigned char volatile xdata *)0xff7d) +#define PWM14T1 (*(unsigned int volatile xdata *)0xff80) +#define PWM14T1H (*(unsigned char volatile xdata *)0xff80) +#define PWM14T1L (*(unsigned char volatile xdata *)0xff81) +#define PWM14T2 (*(unsigned int volatile xdata *)0xff82) +#define PWM14T2H (*(unsigned char volatile xdata *)0xff82) +#define PWM14T2L (*(unsigned char volatile xdata *)0xff83) +#define PWM14CR (*(unsigned char volatile xdata *)0xff84) +#define PWM14HLD (*(unsigned char volatile xdata *)0xff85) +#define PWM15T1 (*(unsigned int volatile xdata *)0xff88) +#define PWM15T1H (*(unsigned char volatile xdata *)0xff88) +#define PWM15T1L (*(unsigned char volatile xdata *)0xff89) +#define PWM15T2 (*(unsigned int volatile xdata *)0xff8a) +#define PWM15T2H (*(unsigned char volatile xdata *)0xff8a) +#define PWM15T2L (*(unsigned char volatile xdata *)0xff8b) +#define PWM15CR (*(unsigned char volatile xdata *)0xff8c) +#define PWM15HLD (*(unsigned char volatile xdata *)0xff8d) +#define PWM16T1 (*(unsigned int volatile xdata *)0xff90) +#define PWM16T1H (*(unsigned char volatile xdata *)0xff90) +#define PWM16T1L (*(unsigned char volatile xdata *)0xff91) +#define PWM16T2 (*(unsigned int volatile xdata *)0xff92) +#define PWM16T2H (*(unsigned char volatile xdata *)0xff92) +#define PWM16T2L (*(unsigned char volatile xdata *)0xff93) +#define PWM16CR (*(unsigned char volatile xdata *)0xff94) +#define PWM16HLD (*(unsigned char volatile xdata *)0xff95) +#define PWM17T1 (*(unsigned int volatile xdata *)0xff98) +#define PWM17T1H (*(unsigned char volatile xdata *)0xff98) +#define PWM17T1L (*(unsigned char volatile xdata *)0xff99) +#define PWM17T2 (*(unsigned int volatile xdata *)0xff9a) +#define PWM17T2H (*(unsigned char volatile xdata *)0xff9a) +#define PWM17T2L (*(unsigned char volatile xdata *)0xff9b) +#define PWM17CR (*(unsigned char volatile xdata *)0xff9c) +#define PWM17HLD (*(unsigned char volatile xdata *)0xff9d) +#define PWM2C (*(unsigned int volatile xdata *)0xffa0) +#define PWM2CH (*(unsigned char volatile xdata *)0xffa0) +#define PWM2CL (*(unsigned char volatile xdata *)0xffa1) +#define PWM2CKS (*(unsigned char volatile xdata *)0xffa2) +#define PWM2TADC (*(unsigned int volatile xdata *)0xffa3) +#define PWM2TADCH (*(unsigned char volatile xdata *)0xffa3) +#define PWM2TADCL (*(unsigned char volatile xdata *)0xffa4) +#define PWM2IF (*(unsigned char volatile xdata *)0xffa5) +#define PWM2FDCR (*(unsigned char volatile xdata *)0xffa6) +#define PWM20T1 (*(unsigned int volatile xdata *)0xffb0) +#define PWM20T1H (*(unsigned char volatile xdata *)0xffb0) +#define PWM20T1L (*(unsigned char volatile xdata *)0xffb1) +#define PWM20T2 (*(unsigned int volatile xdata *)0xffb2) +#define PWM20T2H (*(unsigned char volatile xdata *)0xffb2) +#define PWM20T2L (*(unsigned char volatile xdata *)0xffb3) +#define PWM20CR (*(unsigned char volatile xdata *)0xffb4) +#define PWM20HLD (*(unsigned char volatile xdata *)0xffb5) +#define PWM21T1 (*(unsigned int volatile xdata *)0xffb8) +#define PWM21T1H (*(unsigned char volatile xdata *)0xffb8) +#define PWM21T1L (*(unsigned char volatile xdata *)0xffb9) +#define PWM21T2 (*(unsigned int volatile xdata *)0xffba) +#define PWM21T2H (*(unsigned char volatile xdata *)0xffba) +#define PWM21T2L (*(unsigned char volatile xdata *)0xffbb) +#define PWM21CR (*(unsigned char volatile xdata *)0xffbc) +#define PWM21HLD (*(unsigned char volatile xdata *)0xffbd) +#define PWM22T1 (*(unsigned int volatile xdata *)0xffc0) +#define PWM22T1H (*(unsigned char volatile xdata *)0xffc0) +#define PWM22T1L (*(unsigned char volatile xdata *)0xffc1) +#define PWM22T2 (*(unsigned int volatile xdata *)0xffc2) +#define PWM22T2H (*(unsigned char volatile xdata *)0xffc2) +#define PWM22T2L (*(unsigned char volatile xdata *)0xffc3) +#define PWM22CR (*(unsigned char volatile xdata *)0xffc4) +#define PWM22HLD (*(unsigned char volatile xdata *)0xffc5) +#define PWM23T1 (*(unsigned int volatile xdata *)0xffc8) +#define PWM23T1H (*(unsigned char volatile xdata *)0xffc8) +#define PWM23T1L (*(unsigned char volatile xdata *)0xffc9) +#define PWM23T2 (*(unsigned int volatile xdata *)0xffca) +#define PWM23T2H (*(unsigned char volatile xdata *)0xffca) +#define PWM23T2L (*(unsigned char volatile xdata *)0xffcb) +#define PWM23CR (*(unsigned char volatile xdata *)0xffcc) +#define PWM23HLD (*(unsigned char volatile xdata *)0xffcd) +#define PWM24T1 (*(unsigned int volatile xdata *)0xffd0) +#define PWM24T1H (*(unsigned char volatile xdata *)0xffd0) +#define PWM24T1L (*(unsigned char volatile xdata *)0xffd1) +#define PWM24T2 (*(unsigned int volatile xdata *)0xffd2) +#define PWM24T2H (*(unsigned char volatile xdata *)0xffd2) +#define PWM24T2L (*(unsigned char volatile xdata *)0xffd3) +#define PWM24CR (*(unsigned char volatile xdata *)0xffd4) +#define PWM24HLD (*(unsigned char volatile xdata *)0xffd5) +#define PWM25T1 (*(unsigned int volatile xdata *)0xffd8) +#define PWM25T1H (*(unsigned char volatile xdata *)0xffd8) +#define PWM25T1L (*(unsigned char volatile xdata *)0xffd9) +#define PWM25T2 (*(unsigned int volatile xdata *)0xffda) +#define PWM25T2H (*(unsigned char volatile xdata *)0xffda) +#define PWM25T2L (*(unsigned char volatile xdata *)0xffdb) +#define PWM25CR (*(unsigned char volatile xdata *)0xffdc) +#define PWM25HLD (*(unsigned char volatile xdata *)0xffdd) +#define PWM26T1 (*(unsigned int volatile xdata *)0xffe0) +#define PWM26T1H (*(unsigned char volatile xdata *)0xffe0) +#define PWM26T1L (*(unsigned char volatile xdata *)0xffe1) +#define PWM26T2 (*(unsigned int volatile xdata *)0xffe2) +#define PWM26T2H (*(unsigned char volatile xdata *)0xffe2) +#define PWM26T2L (*(unsigned char volatile xdata *)0xffe3) +#define PWM26CR (*(unsigned char volatile xdata *)0xffe4) +#define PWM26HLD (*(unsigned char volatile xdata *)0xffe5) +#define PWM27T1 (*(unsigned int volatile xdata *)0xffe8) +#define PWM27T1H (*(unsigned char volatile xdata *)0xffe8) +#define PWM27T1L (*(unsigned char volatile xdata *)0xffe9) +#define PWM27T2 (*(unsigned int volatile xdata *)0xffea) +#define PWM27T2H (*(unsigned char volatile xdata *)0xffea) +#define PWM27T2L (*(unsigned char volatile xdata *)0xffeb) +#define PWM27CR (*(unsigned char volatile xdata *)0xffec) +#define PWM27HLD (*(unsigned char volatile xdata *)0xffed) + +///////////////////////////////////////////////// +//FC00H-FCFFH +///////////////////////////////////////////////// + +#define PWM3C (*(unsigned int volatile xdata *)0xfc00) +#define PWM3CH (*(unsigned char volatile xdata *)0xfc00) +#define PWM3CL (*(unsigned char volatile xdata *)0xfc01) +#define PWM3CKS (*(unsigned char volatile xdata *)0xfc02) +#define PWM3IF (*(unsigned char volatile xdata *)0xfc05) +#define PWM3FDCR (*(unsigned char volatile xdata *)0xfc06) +#define PWM30T1 (*(unsigned int volatile xdata *)0xfc10) +#define PWM30T1H (*(unsigned char volatile xdata *)0xfc10) +#define PWM30T1L (*(unsigned char volatile xdata *)0xfc11) +#define PWM30T2 (*(unsigned int volatile xdata *)0xfc12) +#define PWM30T2H (*(unsigned char volatile xdata *)0xfc12) +#define PWM30T2L (*(unsigned char volatile xdata *)0xfc13) +#define PWM30CR (*(unsigned char volatile xdata *)0xfc14) +#define PWM30HLD (*(unsigned char volatile xdata *)0xfc15) +#define PWM31T1 (*(unsigned int volatile xdata *)0xfc18) +#define PWM31T1H (*(unsigned char volatile xdata *)0xfc18) +#define PWM31T1L (*(unsigned char volatile xdata *)0xfc19) +#define PWM31T2 (*(unsigned int volatile xdata *)0xfc1a) +#define PWM31T2H (*(unsigned char volatile xdata *)0xfc1a) +#define PWM31T2L (*(unsigned char volatile xdata *)0xfc1b) +#define PWM31CR (*(unsigned char volatile xdata *)0xfc1c) +#define PWM31HLD (*(unsigned char volatile xdata *)0xfc1d) +#define PWM32T1 (*(unsigned int volatile xdata *)0xfc20) +#define PWM32T1H (*(unsigned char volatile xdata *)0xfc20) +#define PWM32T1L (*(unsigned char volatile xdata *)0xfc21) +#define PWM32T2 (*(unsigned int volatile xdata *)0xfc22) +#define PWM32T2H (*(unsigned char volatile xdata *)0xfc22) +#define PWM32T2L (*(unsigned char volatile xdata *)0xfc23) +#define PWM32CR (*(unsigned char volatile xdata *)0xfc24) +#define PWM32HLD (*(unsigned char volatile xdata *)0xfc25) +#define PWM33T1 (*(unsigned int volatile xdata *)0xfc28) +#define PWM33T1H (*(unsigned char volatile xdata *)0xfc28) +#define PWM33T1L (*(unsigned char volatile xdata *)0xfc29) +#define PWM33T2 (*(unsigned int volatile xdata *)0xfc2a) +#define PWM33T2H (*(unsigned char volatile xdata *)0xfc2a) +#define PWM33T2L (*(unsigned char volatile xdata *)0xfc2b) +#define PWM33CR (*(unsigned char volatile xdata *)0xfc2c) +#define PWM33HLD (*(unsigned char volatile xdata *)0xfc2d) +#define PWM34T1 (*(unsigned int volatile xdata *)0xfc30) +#define PWM34T1H (*(unsigned char volatile xdata *)0xfc30) +#define PWM34T1L (*(unsigned char volatile xdata *)0xfc31) +#define PWM34T2 (*(unsigned int volatile xdata *)0xfc32) +#define PWM34T2H (*(unsigned char volatile xdata *)0xfc32) +#define PWM34T2L (*(unsigned char volatile xdata *)0xfc33) +#define PWM34CR (*(unsigned char volatile xdata *)0xfc34) +#define PWM34HLD (*(unsigned char volatile xdata *)0xfc35) +#define PWM35T1 (*(unsigned int volatile xdata *)0xfc38) +#define PWM35T1H (*(unsigned char volatile xdata *)0xfc38) +#define PWM35T1L (*(unsigned char volatile xdata *)0xfc39) +#define PWM35T2 (*(unsigned int volatile xdata *)0xfc3a) +#define PWM35T2H (*(unsigned char volatile xdata *)0xfc3a) +#define PWM35T2L (*(unsigned char volatile xdata *)0xfc3b) +#define PWM35CR (*(unsigned char volatile xdata *)0xfc3c) +#define PWM35HLD (*(unsigned char volatile xdata *)0xfc3d) +#define PWM36T1 (*(unsigned int volatile xdata *)0xfc40) +#define PWM36T1H (*(unsigned char volatile xdata *)0xfc40) +#define PWM36T1L (*(unsigned char volatile xdata *)0xfc41) +#define PWM36T2 (*(unsigned int volatile xdata *)0xfc42) +#define PWM36T2H (*(unsigned char volatile xdata *)0xfc42) +#define PWM36T2L (*(unsigned char volatile xdata *)0xfc43) +#define PWM36CR (*(unsigned char volatile xdata *)0xfc44) +#define PWM36HLD (*(unsigned char volatile xdata *)0xfc45) +#define PWM37T1 (*(unsigned int volatile xdata *)0xfc48) +#define PWM37T1H (*(unsigned char volatile xdata *)0xfc48) +#define PWM37T1L (*(unsigned char volatile xdata *)0xfc49) +#define PWM37T2 (*(unsigned int volatile xdata *)0xfc4a) +#define PWM37T2H (*(unsigned char volatile xdata *)0xfc4a) +#define PWM37T2L (*(unsigned char volatile xdata *)0xfc4b) +#define PWM37CR (*(unsigned char volatile xdata *)0xfc4c) +#define PWM37HLD (*(unsigned char volatile xdata *)0xfc4d) +#define PWM4C (*(unsigned int volatile xdata *)0xfc50) +#define PWM4CH (*(unsigned char volatile xdata *)0xfc50) +#define PWM4CL (*(unsigned char volatile xdata *)0xfc51) +#define PWM4CKS (*(unsigned char volatile xdata *)0xfc52) +#define PWM4TADC (*(unsigned int volatile xdata *)0xfc53) +#define PWM4TADCH (*(unsigned char volatile xdata *)0xfc53) +#define PWM4TADCL (*(unsigned char volatile xdata *)0xfc54) +#define PWM4IF (*(unsigned char volatile xdata *)0xfc55) +#define PWM4FDCR (*(unsigned char volatile xdata *)0xfc56) +#define PWM40T1 (*(unsigned int volatile xdata *)0xfc60) +#define PWM40T1H (*(unsigned char volatile xdata *)0xfc60) +#define PWM40T1L (*(unsigned char volatile xdata *)0xfc61) +#define PWM40T2 (*(unsigned int volatile xdata *)0xfc62) +#define PWM40T2H (*(unsigned char volatile xdata *)0xfc62) +#define PWM40T2L (*(unsigned char volatile xdata *)0xfc63) +#define PWM40CR (*(unsigned char volatile xdata *)0xfc64) +#define PWM40HLD (*(unsigned char volatile xdata *)0xfc65) +#define PWM41T1 (*(unsigned int volatile xdata *)0xfc68) +#define PWM41T1H (*(unsigned char volatile xdata *)0xfc68) +#define PWM41T1L (*(unsigned char volatile xdata *)0xfc69) +#define PWM41T2 (*(unsigned int volatile xdata *)0xfc6a) +#define PWM41T2H (*(unsigned char volatile xdata *)0xfc6a) +#define PWM41T2L (*(unsigned char volatile xdata *)0xfc6b) +#define PWM41CR (*(unsigned char volatile xdata *)0xfc6c) +#define PWM41HLD (*(unsigned char volatile xdata *)0xfc6d) +#define PWM42T1 (*(unsigned int volatile xdata *)0xfc70) +#define PWM42T1H (*(unsigned char volatile xdata *)0xfc70) +#define PWM42T1L (*(unsigned char volatile xdata *)0xfc71) +#define PWM42T2 (*(unsigned int volatile xdata *)0xfc72) +#define PWM42T2H (*(unsigned char volatile xdata *)0xfc72) +#define PWM42T2L (*(unsigned char volatile xdata *)0xfc73) +#define PWM42CR (*(unsigned char volatile xdata *)0xfc74) +#define PWM42HLD (*(unsigned char volatile xdata *)0xfc75) +#define PWM43T1 (*(unsigned int volatile xdata *)0xfc78) +#define PWM43T1H (*(unsigned char volatile xdata *)0xfc78) +#define PWM43T1L (*(unsigned char volatile xdata *)0xfc79) +#define PWM43T2 (*(unsigned int volatile xdata *)0xfc7a) +#define PWM43T2H (*(unsigned char volatile xdata *)0xfc7a) +#define PWM43T2L (*(unsigned char volatile xdata *)0xfc7b) +#define PWM43CR (*(unsigned char volatile xdata *)0xfc7c) +#define PWM43HLD (*(unsigned char volatile xdata *)0xfc7d) +#define PWM44T1 (*(unsigned int volatile xdata *)0xfc80) +#define PWM44T1H (*(unsigned char volatile xdata *)0xfc80) +#define PWM44T1L (*(unsigned char volatile xdata *)0xfc81) +#define PWM44T2 (*(unsigned int volatile xdata *)0xfc82) +#define PWM44T2H (*(unsigned char volatile xdata *)0xfc82) +#define PWM44T2L (*(unsigned char volatile xdata *)0xfc83) +#define PWM44CR (*(unsigned char volatile xdata *)0xfc84) +#define PWM44HLD (*(unsigned char volatile xdata *)0xfc85) +#define PWM45T1 (*(unsigned int volatile xdata *)0xfc88) +#define PWM45T1H (*(unsigned char volatile xdata *)0xfc88) +#define PWM45T1L (*(unsigned char volatile xdata *)0xfc89) +#define PWM45T2 (*(unsigned int volatile xdata *)0xfc8a) +#define PWM45T2H (*(unsigned char volatile xdata *)0xfc8a) +#define PWM45T2L (*(unsigned char volatile xdata *)0xfc8b) +#define PWM45CR (*(unsigned char volatile xdata *)0xfc8c) +#define PWM45HLD (*(unsigned char volatile xdata *)0xfc8d) +#define PWM46T1 (*(unsigned int volatile xdata *)0xfc90) +#define PWM46T1H (*(unsigned char volatile xdata *)0xfc90) +#define PWM46T1L (*(unsigned char volatile xdata *)0xfc91) +#define PWM46T2 (*(unsigned int volatile xdata *)0xfc92) +#define PWM46T2H (*(unsigned char volatile xdata *)0xfc92) +#define PWM46T2L (*(unsigned char volatile xdata *)0xfc93) +#define PWM46CR (*(unsigned char volatile xdata *)0xfc94) +#define PWM46HLD (*(unsigned char volatile xdata *)0xfc95) +#define PWM47T1 (*(unsigned int volatile xdata *)0xfc98) +#define PWM47T1H (*(unsigned char volatile xdata *)0xfc98) +#define PWM47T1L (*(unsigned char volatile xdata *)0xfc99) +#define PWM47T2 (*(unsigned int volatile xdata *)0xfc9a) +#define PWM47T2H (*(unsigned char volatile xdata *)0xfc9a) +#define PWM47T2L (*(unsigned char volatile xdata *)0xfc9b) +#define PWM47CR (*(unsigned char volatile xdata *)0xfc9c) +#define PWM47HLD (*(unsigned char volatile xdata *)0xfc9d) +#define PWM5C (*(unsigned int volatile xdata *)0xfca0) +#define PWM5CH (*(unsigned char volatile xdata *)0xfca0) +#define PWM5CL (*(unsigned char volatile xdata *)0xfca1) +#define PWM5CKS (*(unsigned char volatile xdata *)0xfca2) +#define PWM5IF (*(unsigned char volatile xdata *)0xfca5) +#define PWM5FDCR (*(unsigned char volatile xdata *)0xfca6) +#define PWM50T1 (*(unsigned int volatile xdata *)0xfcb0) +#define PWM50T1H (*(unsigned char volatile xdata *)0xfcb0) +#define PWM50T1L (*(unsigned char volatile xdata *)0xfcb1) +#define PWM50T2 (*(unsigned int volatile xdata *)0xfcb2) +#define PWM50T2H (*(unsigned char volatile xdata *)0xfcb2) +#define PWM50T2L (*(unsigned char volatile xdata *)0xfcb3) +#define PWM50CR (*(unsigned char volatile xdata *)0xfcb4) +#define PWM50HLD (*(unsigned char volatile xdata *)0xfcb5) +#define PWM51T1 (*(unsigned int volatile xdata *)0xfcb8) +#define PWM51T1H (*(unsigned char volatile xdata *)0xfcb8) +#define PWM51T1L (*(unsigned char volatile xdata *)0xfcb9) +#define PWM51T2 (*(unsigned int volatile xdata *)0xfcba) +#define PWM51T2H (*(unsigned char volatile xdata *)0xfcba) +#define PWM51T2L (*(unsigned char volatile xdata *)0xfcbb) +#define PWM51CR (*(unsigned char volatile xdata *)0xfcbc) +#define PWM51HLD (*(unsigned char volatile xdata *)0xfcbd) +#define PWM52T1 (*(unsigned int volatile xdata *)0xfcc0) +#define PWM52T1H (*(unsigned char volatile xdata *)0xfcc0) +#define PWM52T1L (*(unsigned char volatile xdata *)0xfcc1) +#define PWM52T2 (*(unsigned int volatile xdata *)0xfcc2) +#define PWM52T2H (*(unsigned char volatile xdata *)0xfcc2) +#define PWM52T2L (*(unsigned char volatile xdata *)0xfcc3) +#define PWM52CR (*(unsigned char volatile xdata *)0xfcc4) +#define PWM52HLD (*(unsigned char volatile xdata *)0xfcc5) +#define PWM53T1 (*(unsigned int volatile xdata *)0xfcc8) +#define PWM53T1H (*(unsigned char volatile xdata *)0xfcc8) +#define PWM53T1L (*(unsigned char volatile xdata *)0xfcc9) +#define PWM53T2 (*(unsigned int volatile xdata *)0xfcca) +#define PWM53T2H (*(unsigned char volatile xdata *)0xfcca) +#define PWM53T2L (*(unsigned char volatile xdata *)0xfccb) +#define PWM53CR (*(unsigned char volatile xdata *)0xfccc) +#define PWM53HLD (*(unsigned char volatile xdata *)0xfccd) +#define PWM54T1 (*(unsigned int volatile xdata *)0xfcd0) +#define PWM54T1H (*(unsigned char volatile xdata *)0xfcd0) +#define PWM54T1L (*(unsigned char volatile xdata *)0xfcd1) +#define PWM54T2 (*(unsigned int volatile xdata *)0xfcd2) +#define PWM54T2H (*(unsigned char volatile xdata *)0xfcd2) +#define PWM54T2L (*(unsigned char volatile xdata *)0xfcd3) +#define PWM54CR (*(unsigned char volatile xdata *)0xfcd4) +#define PWM54HLD (*(unsigned char volatile xdata *)0xfcd5) +#define PWM55T1 (*(unsigned int volatile xdata *)0xfcd8) +#define PWM55T1H (*(unsigned char volatile xdata *)0xfcd8) +#define PWM55T1L (*(unsigned char volatile xdata *)0xfcd9) +#define PWM55T2 (*(unsigned int volatile xdata *)0xfcda) +#define PWM55T2H (*(unsigned char volatile xdata *)0xfcda) +#define PWM55T2L (*(unsigned char volatile xdata *)0xfcdb) +#define PWM55CR (*(unsigned char volatile xdata *)0xfcdc) +#define PWM55HLD (*(unsigned char volatile xdata *)0xfcdd) +#define PWM56T1 (*(unsigned int volatile xdata *)0xfce0) +#define PWM56T1H (*(unsigned char volatile xdata *)0xfce0) +#define PWM56T1L (*(unsigned char volatile xdata *)0xfce1) +#define PWM56T2 (*(unsigned int volatile xdata *)0xfce2) +#define PWM56T2H (*(unsigned char volatile xdata *)0xfce2) +#define PWM56T2L (*(unsigned char volatile xdata *)0xfce3) +#define PWM56CR (*(unsigned char volatile xdata *)0xfce4) +#define PWM56HLD (*(unsigned char volatile xdata *)0xfce5) +#define PWM57T1 (*(unsigned int volatile xdata *)0xfce8) +#define PWM57T1H (*(unsigned char volatile xdata *)0xfce8) +#define PWM57T1L (*(unsigned char volatile xdata *)0xfce9) +#define PWM57T2 (*(unsigned int volatile xdata *)0xfcea) +#define PWM57T2H (*(unsigned char volatile xdata *)0xfcea) +#define PWM57T2L (*(unsigned char volatile xdata *)0xfceb) +#define PWM57CR (*(unsigned char volatile xdata *)0xfcec) +#define PWM57HLD (*(unsigned char volatile xdata *)0xfced) + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMSET = 0xF1H; ENGLBSET PWMRST ENPWM5 ENPWM4 ENPWM3 ENPWM2 ENPWM1 ENPWM0 0000,0000 /* ÔöÇ¿ÐÍPWMÈ«¾ÖÅäÖüĴæÆ÷ */ +#define PWM15_SET_Uniform() PWMSET |= 0x80 //1£º6×éPWM²ÉÓÃͳһµÄÉèÖ÷½Ê½ +#define PWM15_SET_Independent() PWMSET &= ~0x80 //0£º6×éPWM²ÉÓø÷×Ô¶ÀÁ¢µÄÉèÖ÷½Ê½ + +#define PWM15_Reset() PWMSET |= 0x40 //1£º¸´Î»ËùÓÐPWMµÄXFR¼Ä´æÆ÷£¬SFR²»±ä + +#define PWM15_PWM5_Enable() PWMSET |= 0x20 //1£ºÊ¹ÄÜPWM5£¨°üÀ¨ PWM50~PWM54£©¡£ +#define PWM15_PWM5_Disable() PWMSET &= ~0x20 //0£º¹Ø±ÕPWM5 + +#define PWM15_PWM4_Enable() PWMSET |= 0x10 //1£ºÊ¹ÄÜPWM4£¨°üÀ¨ PWM40~PWM47£©¡£ +#define PWM15_PWM4_Disable() PWMSET &= ~0x10 //0£º¹Ø±ÕPWM4 + +#define PWM15_PWM3_Enable() PWMSET |= 0x08 //1£ºÊ¹ÄÜPWM3£¨°üÀ¨ PWM30~PWM37£©¡£ +#define PWM15_PWM3_Disable() PWMSET &= ~0x08 //0£º¹Ø±ÕPWM3 + +#define PWM15_PWM2_Enable() PWMSET |= 0x04 //1£ºÊ¹ÄÜPWM2£¨°üÀ¨ PWM20~PWM27£©¡£ +#define PWM15_PWM2_Disable() PWMSET &= ~0x04 //0£º¹Ø±ÕPWM2 + +#define PWM15_PWM1_Enable() PWMSET |= 0x02 //1£ºÊ¹ÄÜPWM1£¨°üÀ¨ PWM10~PWM17£©¡£ +#define PWM15_PWM1_Disable() PWMSET &= ~0x02 //0£º¹Ø±ÕPWM1 + +#define PWM15_PWM0_Enable() PWMSET |= 0x01 //1£ºÊ¹ÄÜPWM0£¨°üÀ¨ PWM00~PWM07£©¡£ +#define PWM15_PWM0_Disable() PWMSET &= ~0x01 //0£º¹Ø±ÕPWM0 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMCFG01= 0xF6H; PWM1CBIF EPWM1CBI FLTPS0 PWM1CEN PWM0CBIF EPWM0CBI ENPWM0TA PWM0CEN 0000,0000 /* ÔöÇ¿ÐÍPWMÅäÖüĴæÆ÷ */ +//sfr PWMCFG23= 0xF7H; PWM3CBIF EPWM3CBI FLTPS1 PWM3CEN PWM2CBIF EPWM2CBI ENPWM2TA PWM2CEN 0000,0000 /* ÔöÇ¿ÐÍPWMÅäÖüĴæÆ÷ */ +//sfr PWMCFG45= 0xFEH; PWM5CBIF EPWM5CBI FLTPS2 PWM5CEN PWM4CBIF EPWM4CBI ENPWM4TA PWM4CEN 0000,0000 /* ÔöÇ¿ÐÍPWMÅäÖüĴæÆ÷ */ +#define PWM1CBIF 0x80 +#define PWM0CBIF 0x08 +#define FLTPSn 0x20 + +#define PWM15_Counter1Int_Enable() PWMCFG01 |= 0x40 //1£ºÊ¹ÄܼÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter1Int_Disable() PWMCFG01 &= ~0x40 //0£º¹Ø±Õ¼ÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter1_Enable() PWMCFG01 |= 0x10 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWM15_Counter1_Disable() PWMCFG01 &= ~0x10 //0£º¹Ø±Õ¼ÆÊýÆ÷ +#define PWM15_Counter0Int_Enable() PWMCFG01 |= 0x04 //1£ºÊ¹ÄܼÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter0Int_Disable() PWMCFG01 &= ~0x04 //0£º¹Ø±Õ¼ÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter0_Enable() PWMCFG01 |= 0x01 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWM15_Counter0_Disable() PWMCFG01 &= ~0x01 //0£º¹Ø±Õ¼ÆÊýÆ÷ +#define PWM15_PWM0_ADC_Enable() PWMCFG01 |= 0x02 //1£ºPWMÓëADCÏà¹ØÁª +#define PWM15_PWM0_ADC_Disable() PWMCFG01 &= ~0x02 //0£ºPWMÓëADC²»¹ØÁª + +#define PWM15_Counter3Int_Enable() PWMCFG23 |= 0x40 //1£ºÊ¹ÄܼÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter3Int_Disable() PWMCFG23 &= ~0x40 //0£º¹Ø±Õ¼ÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter3_Enable() PWMCFG23 |= 0x10 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWM15_Counter3_Disable() PWMCFG23 &= ~0x10 //0£º¹Ø±Õ¼ÆÊýÆ÷ +#define PWM15_Counter2Int_Enable() PWMCFG23 |= 0x04 //1£ºÊ¹ÄܼÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter2Int_Disable() PWMCFG23 &= ~0x04 //0£º¹Ø±Õ¼ÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter2_Enable() PWMCFG23 |= 0x01 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWM15_Counter2_Disable() PWMCFG23 &= ~0x01 //0£º¹Ø±Õ¼ÆÊýÆ÷ +#define PWM15_PWM2_ADC_Enable() PWMCFG23 |= 0x02 //1£ºPWMÓëADCÏà¹ØÁª +#define PWM15_PWM2_ADC_Disable() PWMCFG23 &= ~0x02 //0£ºPWMÓëADC²»¹ØÁª + +#define PWM15_Counter5Int_Enable() PWMCFG45 |= 0x40 //1£ºÊ¹ÄܼÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter5Int_Disable() PWMCFG45 &= ~0x40 //0£º¹Ø±Õ¼ÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter5_Enable() PWMCFG45 |= 0x10 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWM15_Counter5_Disable() PWMCFG45 &= ~0x10 //0£º¹Ø±Õ¼ÆÊýÆ÷ +#define PWM15_Counter4Int_Enable() PWMCFG45 |= 0x04 //1£ºÊ¹ÄܼÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter4Int_Disable() PWMCFG45 &= ~0x04 //0£º¹Ø±Õ¼ÆÊýÆ÷¹éÁãÖÐ¶Ï +#define PWM15_Counter4_Enable() PWMCFG45 |= 0x01 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWM15_Counter4_Disable() PWMCFG45 &= ~0x01 //0£º¹Ø±Õ¼ÆÊýÆ÷ +#define PWM15_PWM4_ADC_Enable() PWMCFG45 |= 0x02 //1£ºPWMÓëADCÏà¹ØÁª +#define PWM15_PWM4_ADC_Disable() PWMCFG45 &= ~0x02 //0£ºPWMÓëADC²»¹ØÁª + +/* PWMnIF */ +#define C7IF = (1<<7) +#define C6IF = (1<<6) +#define C5IF = (1<<5) +#define C4IF = (1<<4) +#define C3IF = (1<<3) +#define C2IF = (1<<2) +#define C1IF = (1<<1) +#define C0IF = 1 + +/* PWMnFDCR */ +#define INVCMP = (1<<7) +#define INVIO = (1<<6) +#define ENFD = (1<<5) +#define FLTFLIO = (1<<4) +#define EFDI = (1<<3) +#define FDCMP = (1<<2) +#define FDIO = (1<<1) +#define FDIF = 1 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWM0CKS = 0xFF02H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ÔöÇ¿ÐÍPWMʱÖÓÑ¡Ôñ´æÆ÷ */ +//sfr PWM1CKS = 0xFF52H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ÔöÇ¿ÐÍPWMʱÖÓÑ¡Ôñ´æÆ÷ */ +//sfr PWM2CKS = 0xFFA2H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ÔöÇ¿ÐÍPWMʱÖÓÑ¡Ôñ´æÆ÷ */ +//sfr PWM3CKS = 0xFC02H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ÔöÇ¿ÐÍPWMʱÖÓÑ¡Ôñ´æÆ÷ */ +//sfr PWM4CKS = 0xFC52H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ÔöÇ¿ÐÍPWMʱÖÓÑ¡Ôñ´æÆ÷ */ +//sfr PWM5CKS = 0xFCA2H; - - - SELT2 PWM_PS[3:0] xxx0,0000 /* ÔöÇ¿ÐÍPWMʱÖÓÑ¡Ôñ´æÆ÷ */ +#define PWM0_PS_Clock() PWM0CKS &= ~0x10 //0£ºPWMnʱÖÓԴΪϵͳʱÖÓ·ÖƵºóµÄʱÖÓ +#define PWM0_T2_Clock() PWM0CKS |= 0x10 //1£ºPWMnʱÖÓԴΪ¶¨Ê±Æ÷2µÄÒç³öÂö³å +#define PWM0_PS_Set(n) PWM0CKS = (PWM0CKS & ~0x0F) | (n & 0x0F) //ϵͳʱÖÓÔ¤·ÖƵ²ÎÊýÉèÖãºSYSclk / (PWM_PS+1) +#define PWM1_PS_Clock() PWM1CKS &= ~0x10 //0£ºPWMnʱÖÓԴΪϵͳʱÖÓ·ÖƵºóµÄʱÖÓ +#define PWM1_T2_Clock() PWM1CKS |= 0x10 //1£ºPWMnʱÖÓԴΪ¶¨Ê±Æ÷2µÄÒç³öÂö³å +#define PWM1_PS_Set(n) PWM1CKS = (PWM1CKS & ~0x0F) | (n & 0x0F) //ϵͳʱÖÓÔ¤·ÖƵ²ÎÊýÉèÖãºSYSclk / (PWM_PS+1) +#define PWM2_PS_Clock() PWM2CKS &= ~0x10 //0£ºPWMnʱÖÓԴΪϵͳʱÖÓ·ÖƵºóµÄʱÖÓ +#define PWM2_T2_Clock() PWM2CKS |= 0x10 //1£ºPWMnʱÖÓԴΪ¶¨Ê±Æ÷2µÄÒç³öÂö³å +#define PWM2_PS_Set(n) PWM2CKS = (PWM2CKS & ~0x0F) | (n & 0x0F) //ϵͳʱÖÓÔ¤·ÖƵ²ÎÊýÉèÖãºSYSclk / (PWM_PS+1) +#define PWM3_PS_Clock() PWM3CKS &= ~0x10 //0£ºPWMnʱÖÓԴΪϵͳʱÖÓ·ÖƵºóµÄʱÖÓ +#define PWM3_T2_Clock() PWM3CKS |= 0x10 //1£ºPWMnʱÖÓԴΪ¶¨Ê±Æ÷2µÄÒç³öÂö³å +#define PWM3_PS_Set(n) PWM3CKS = (PWM3CKS & ~0x0F) | (n & 0x0F) //ϵͳʱÖÓÔ¤·ÖƵ²ÎÊýÉèÖãºSYSclk / (PWM_PS+1) +#define PWM4_PS_Clock() PWM4CKS &= ~0x10 //0£ºPWMnʱÖÓԴΪϵͳʱÖÓ·ÖƵºóµÄʱÖÓ +#define PWM4_T2_Clock() PWM4CKS |= 0x10 //1£ºPWMnʱÖÓԴΪ¶¨Ê±Æ÷2µÄÒç³öÂö³å +#define PWM4_PS_Set(n) PWM4CKS = (PWM4CKS & ~0x0F) | (n & 0x0F) //ϵͳʱÖÓÔ¤·ÖƵ²ÎÊýÉèÖãºSYSclk / (PWM_PS+1) +#define PWM5_PS_Clock() PWM5CKS &= ~0x10 //0£ºPWMnʱÖÓԴΪϵͳʱÖÓ·ÖƵºóµÄʱÖÓ +#define PWM5_T2_Clock() PWM5CKS |= 0x10 //1£ºPWMnʱÖÓԴΪ¶¨Ê±Æ÷2µÄÒç³öÂö³å +#define PWM5_PS_Set(n) PWM5CKS = (PWM5CKS & ~0x0F) | (n & 0x0F) //ϵͳʱÖÓÔ¤·ÖƵ²ÎÊýÉèÖãºSYSclk / (PWM_PS+1) + +/* PWMnTADC */ +#define PWM15_PWM0TADC(n) PWM0TADC = (n & 0x7fff) //PWM´¥·¢ADCʱ¼äµã +#define PWM15_PWM2TADC(n) PWM2TADC = (n & 0x7fff) //PWM´¥·¢ADCʱ¼äµã +#define PWM15_PWM4TADC(n) PWM4TADC = (n & 0x7fff) //PWM´¥·¢ADCʱ¼äµã + +/* PWMnTADC */ +#define PWM15_PWM0TADC(n) PWM0TADC = (n & 0x7fff) //PWM´¥·¢ADCʱ¼äµã + + +/* BIT Registers */ +/* PSW */ +sbit CY = PSW^7; +sbit AC = PSW^6; +sbit F0 = PSW^5; +sbit RS1 = PSW^4; +sbit RS0 = PSW^3; +sbit OV = PSW^2; +sbit F1 = PSW^1; +sbit P = PSW^0; + +/* TCON */ +sbit TF1 = TCON^7; //¶¨Ê±Æ÷1Òç³öÖжϱê־λ +sbit TR1 = TCON^6; //¶¨Ê±Æ÷1ÔËÐпØÖÆλ +sbit TF0 = TCON^5; //¶¨Ê±Æ÷0Òç³öÖжϱê־λ +sbit TR0 = TCON^4; //¶¨Ê±Æ÷0ÔËÐпØÖÆλ +sbit IE1 = TCON^3; //ÍâÖжÏ1±ê־λ +sbit IT1 = TCON^2; //ÍâÖжÏ1Ðźŷ½Ê½¿ØÖÆ룬1£ºÏ½µÑØÖжϣ¬0£ºÉÏÉýϽµ¾ùÖжϡ£ +sbit IE0 = TCON^1; //ÍâÖжÏ0±ê־λ +sbit IT0 = TCON^0; //ÍâÖжÏ0Ðźŷ½Ê½¿ØÖÆ룬1£ºÏ½µÑØÖжϣ¬0£ºÉÏÉýϽµ¾ùÖжϡ£ + +/* P0 */ +sbit P00 = P0^0; +sbit P01 = P0^1; +sbit P02 = P0^2; +sbit P03 = P0^3; +sbit P04 = P0^4; +sbit P05 = P0^5; +sbit P06 = P0^6; +sbit P07 = P0^7; + +/* P1 */ +sbit P10 = P1^0; +sbit P11 = P1^1; +sbit P12 = P1^2; +sbit P13 = P1^3; +sbit P14 = P1^4; +sbit P15 = P1^5; +sbit P16 = P1^6; +sbit P17 = P1^7; + +sbit RXD2 = P1^0; +sbit TXD2 = P1^1; +sbit CCP1 = P1^0; +sbit CCP0 = P1^1; +sbit SPI_SS = P1^2; +sbit SPI_MOSI = P1^3; +sbit SPI_MISO = P1^4; +sbit SPI_SCLK = P1^5; + +sbit SPI_SS_2 = P2^2; +sbit SPI_MOSI_2 = P2^3; +sbit SPI_MISO_2 = P2^4; +sbit SPI_SCLK_2 = P2^5; + +sbit SPI_SS_3 = P5^4; +sbit SPI_MOSI_3 = P4^0; +sbit SPI_MISO_3 = P4^1; +sbit SPI_SCLK_3 = P4^3; + +sbit SPI_SS_4 = P3^5; +sbit SPI_MOSI_4 = P3^4; +sbit SPI_MISO_4 = P3^3; +sbit SPI_SCLK_4 = P3^2; + +/* P2 */ +sbit P20 = P2^0; +sbit P21 = P2^1; +sbit P22 = P2^2; +sbit P23 = P2^3; +sbit P24 = P2^4; +sbit P25 = P2^5; +sbit P26 = P2^6; +sbit P27 = P2^7; + +/* P3 */ +sbit P30 = P3^0; +sbit P31 = P3^1; +sbit P32 = P3^2; +sbit P33 = P3^3; +sbit P34 = P3^4; +sbit P35 = P3^5; +sbit P36 = P3^6; +sbit P37 = P3^7; + +sbit RXD = P3^0; +sbit TXD = P3^1; +sbit INT0 = P3^2; +sbit INT1 = P3^3; +sbit T0 = P3^4; +sbit T1 = P3^5; +sbit WR = P3^6; +sbit RD = P3^7; + +sbit INT2 = P3^6; +sbit INT3 = P3^7; +sbit INT4 = P3^0; +sbit CCP2 = P3^7; + +sbit CLKOUT0 = P3^5; +sbit CLKOUT1 = P3^4; + +/* P4 */ +sbit P40 = P4^0; +sbit P41 = P4^1; +sbit P42 = P4^2; +sbit P43 = P4^3; +sbit P44 = P4^4; +sbit P45 = P4^5; +sbit P46 = P4^6; +sbit P47 = P4^7; + +/* P5 */ +sbit P50 = P5^0; +sbit P51 = P5^1; +sbit P52 = P5^2; +sbit P53 = P5^3; +sbit P54 = P5^4; +sbit P55 = P5^5; +sbit P56 = P5^6; +sbit P57 = P5^7; + +/* P6 */ +sbit P60 = P6^0; +sbit P61 = P6^1; +sbit P62 = P6^2; +sbit P63 = P6^3; +sbit P64 = P6^4; +sbit P65 = P6^5; +sbit P66 = P6^6; +sbit P67 = P6^7; + +/* P7 */ +sbit P70 = P7^0; +sbit P71 = P7^1; +sbit P72 = P7^2; +sbit P73 = P7^3; +sbit P74 = P7^4; +sbit P75 = P7^5; +sbit P76 = P7^6; +sbit P77 = P7^7; + + +/* SCON */ +sbit SM0 = SCON^7; //SM0/FE SM0 SM1 = 00 ~ 11: ·½Ê½0~3 +sbit SM1 = SCON^6; // +sbit SM2 = SCON^5; //¶à»úͨѶ +sbit REN = SCON^4; //½ÓÊÕÔÊÐí +sbit TB8 = SCON^3; //·¢ËÍÊý¾ÝµÚ8λ +sbit RB8 = SCON^2; //½ÓÊÕÊý¾ÝµÚ8λ +sbit TI = SCON^1; //·¢ËÍÖжϱê־λ +sbit RI = SCON^0; //½ÓÊÕÖжϱê־λ + +/* IE */ +sbit EA = IE^7; //ÖжÏÔÊÐí×Ü¿ØÖÆλ +sbit ELVD = IE^6; //µÍѹ¼à²âÖжÏÔÊÐíλ +sbit EADC = IE^5; //ADC ÖÐ¶Ï ÔÊÐíλ +sbit ES = IE^4; //´®ÐÐÖÐ¶Ï ÔÊÐí¿ØÖÆλ +sbit ET1 = IE^3; //¶¨Ê±ÖжÏ1ÔÊÐí¿ØÖÆλ +sbit EX1 = IE^2; //ÍⲿÖжÏ1ÔÊÐí¿ØÖÆλ +sbit ET0 = IE^1; //¶¨Ê±ÖжÏ0ÔÊÐí¿ØÖÆλ +sbit EX0 = IE^0; //ÍⲿÖжÏ0ÔÊÐí¿ØÖÆλ + +sbit ACC0 = ACC^0; +sbit ACC1 = ACC^1; +sbit ACC2 = ACC^2; +sbit ACC3 = ACC^3; +sbit ACC4 = ACC^4; +sbit ACC5 = ACC^5; +sbit ACC6 = ACC^6; +sbit ACC7 = ACC^7; + +sbit B0 = B^0; +sbit B1 = B^1; +sbit B2 = B^2; +sbit B3 = B^3; +sbit B4 = B^4; +sbit B5 = B^5; +sbit B6 = B^6; +sbit B7 = B^7; + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IE2 = 0xAF; ETKSUI ET4 ET3 ES4 ES3 ET2 ESPI ES2 x000,0000B //Auxiliary Interrupt +#define SPI_INT_ENABLE() IE2 |= 2 /* ÔÊÐíSPIÖÐ¶Ï */ +#define SPI_INT_DISABLE() IE2 &= ~2 /* ÔÊÐíSPIÖÐ¶Ï */ +#define UART2_INT_ENABLE() IE2 |= 1 /* ÔÊÐí´®¿Ú2ÖÐ¶Ï */ +#define UART2_INT_DISABLE() IE2 &= ~1 /* ÔÊÐí´®¿Ú2ÖÐ¶Ï */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP2 = 0xB5; // PPWM2FD PI2C PCMP PX4 PPWM0FD PPWM0 PSPI PS2 0000,0000 +#define PUSB 0x80 +#define PPWM2FD 0x80 +#define PTKSU 0x80 +#define PI2C 0x40 +#define PCMP 0x20 +#define PX4 0x10 +#define PPWM0FD 0x08 +#define PPWM0 0x04 +#define PSPI 0x02 +#define PS2 0x01 +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP2H = 0xB6; // PPWM2FDH PI2CH PCMPH PX4H PPWM0FDH PPWM0H PSPIH PS2H 0000,0000 +#define PUSBH 0x80 +#define PPWM2FDH 0x80 +#define PTKSUH 0x80 +#define PI2CH 0x40 +#define PCMPH 0x20 +#define PX4H 0x10 +#define PPWM0FDH 0x08 +#define PPWM0H 0x04 +#define PSPIH 0x02 +#define PS2H 0x01 + +//´®¿Ú2ÖжÏÓÅÏȼ¶¿ØÖÆ +#define UART2_Priority(n) do{if(n == 0) IP2H &= ~PS2H, IP2 &= ~PS2; \ + if(n == 1) IP2H &= ~PS2H, IP2 |= PS2; \ + if(n == 2) IP2H |= PS2H, IP2 &= ~PS2; \ + if(n == 3) IP2H |= PS2H, IP2 |= PS2; \ + }while(0) +//SPIÖжÏÓÅÏȼ¶¿ØÖÆ +#define SPI_Priority(n) do{if(n == 0) IP2H &= ~PSPIH, IP2 &= ~PSPI; \ + if(n == 1) IP2H &= ~PSPIH, IP2 |= PSPI; \ + if(n == 2) IP2H |= PSPIH, IP2 &= ~PSPI; \ + if(n == 3) IP2H |= PSPIH, IP2 |= PSPI; \ + }while(0) +//ÍⲿÖжÏ4ÖжÏÓÅÏȼ¶¿ØÖÆ +#define INT4_Priority(n) do{if(n == 0) IP2H &= ~PX4H, IP2 &= ~PX4; \ + if(n == 1) IP2H &= ~PX4H, IP2 |= PX4; \ + if(n == 2) IP2H |= PX4H, IP2 &= ~PX4; \ + if(n == 3) IP2H |= PX4H, IP2 |= PX4; \ + }while(0) +//±È½ÏÆ÷ÖжÏÓÅÏȼ¶¿ØÖÆ +#define CMP_Priority(n) do{if(n == 0) IP2H &= ~PCMPH, IP2 &= ~PCMP; \ + if(n == 1) IP2H &= ~PCMPH, IP2 |= PCMP; \ + if(n == 2) IP2H |= PCMPH, IP2 &= ~PCMP; \ + if(n == 3) IP2H |= PCMPH, IP2 |= PCMP; \ + }while(0) +//I2CÖжÏÓÅÏȼ¶¿ØÖÆ +#define I2C_Priority(n) do{if(n == 0) IP2H &= ~PI2CH, IP2 &= ~PI2C; \ + if(n == 1) IP2H &= ~PI2CH, IP2 |= PI2C; \ + if(n == 2) IP2H |= PI2CH, IP2 &= ~PI2C; \ + if(n == 3) IP2H |= PI2CH, IP2 |= PI2C; \ + }while(0) +//ÔöÇ¿ÐÍPWM0ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM0_Priority(n) do{if(n == 0) IP2H &= ~PPWM0H, IP2 &= ~PPWM0; \ + if(n == 1) IP2H &= ~PPWM0H, IP2 |= PPWM0; \ + if(n == 2) IP2H |= PPWM0H, IP2 &= ~PPWM0; \ + if(n == 3) IP2H |= PPWM0H, IP2 |= PPWM0; \ + }while(0) +//ÔöÇ¿ÐÍPWM0Òì³£¼ì²âÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM0FD_Priority(n) do{if(n == 0) IP2H &= ~PPWM0FDH, IP2 &= ~PPWM0FD; \ + if(n == 1) IP2H &= ~PPWM0FDH, IP2 |= PPWM0FD; \ + if(n == 2) IP2H |= PPWM0FDH, IP2 &= ~PPWM0FD; \ + if(n == 3) IP2H |= PPWM0FDH, IP2 |= PPWM0FD; \ + }while(0) +//ÔöÇ¿ÐÍPWM2Òì³£¼ì²âÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM2FD_Priority(n) do{if(n == 0) IP2H &= ~PPWM2FDH, IP2 &= ~PPWM2FD; \ + if(n == 1) IP2H &= ~PPWM2FDH, IP2 |= PPWM2FD; \ + if(n == 2) IP2H |= PPWM2FDH, IP2 &= ~PPWM2FD; \ + if(n == 3) IP2H |= PPWM2FDH, IP2 |= PPWM2FD; \ + }while(0) +//´¥Ãþ°´¼üÖжÏÓÅÏȼ¶¿ØÖÆ +#define PTKSU_Priority(n) do{if(n == 0) IP2H &= ~PTKSUH, IP2 &= ~PTKSU; \ + if(n == 1) IP2H &= ~PTKSUH, IP2 |= PTKSU; \ + if(n == 2) IP2H |= PTKSUH, IP2 &= ~PTKSU; \ + if(n == 3) IP2H |= PTKSUH, IP2 |= PTKSU; \ + }while(0) + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP3 = 0xDF; // PPWM4FD PPWM5 PPWM4 PPWM3 PPWM2 PPWM1 PS4 PS3 0000,0000 +#define PPWM4FD 0x80 +#define PPWM5 0x40 +#define PPWM4 0x20 +#define PPWM3 0x10 +#define PPWM2 0x08 +#define PPWM1 0x04 +#define PRTC 0x04 +#define PS4 0x02 +#define PS3 0x01 +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP3H = 0xEE; // PPWM4FDH PPWM5H PPWM4H PPWM3H PPWM2H PPWM1H PS4H PS3H 0000,0000 +#define PPWM4FDH 0x80 +#define PPWM5H 0x40 +#define PPWM4H 0x20 +#define PPWM3H 0x10 +#define PPWM2H 0x08 +#define PPWM1H 0x04 +#define PRTCH 0x04 +#define PS4H 0x02 +#define PS3H 0x01 + +#ifdef STC8Hxx + +//ÔöÇ¿ÐÍPWM1ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM1_Priority(n) do{if(n == 0) IP2H &= ~PPWM1H, IP2 &= ~PPWM1; \ + if(n == 1) IP2H &= ~PPWM1H, IP2 |= PPWM1; \ + if(n == 2) IP2H |= PPWM1H, IP2 &= ~PPWM1; \ + if(n == 3) IP2H |= PPWM1H, IP2 |= PPWM1; \ + }while(0) +//ÔöÇ¿ÐÍPWM2ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM2_Priority(n) do{if(n == 0) IP2H &= ~PPWM2H, IP2 &= ~PPWM2; \ + if(n == 1) IP2H &= ~PPWM2H, IP2 |= PPWM2; \ + if(n == 2) IP2H |= PPWM2H, IP2 &= ~PPWM2; \ + if(n == 3) IP2H |= PPWM2H, IP2 |= PPWM2; \ + }while(0) +//USBÖжÏÓÅÏȼ¶¿ØÖÆ +#define USB_Priority(n) do{if(n == 0) IP2H &= ~PUSBH, IP2 &= ~PUSB; \ + if(n == 1) IP2H &= ~PUSBH, IP2 |= PUSB; \ + if(n == 2) IP2H |= PUSBH, IP2 &= ~PUSB; \ + if(n == 3) IP2H |= PUSBH, IP2 |= PUSB; \ + }while(0) +//RTCÖжÏÓÅÏȼ¶¿ØÖÆ +#define RTC_Priority(n) do{if(n == 0) IP3H &= ~PRTCH, IP3 &= ~PRTC; \ + if(n == 1) IP3H &= ~PRTCH, IP3 |= PRTC; \ + if(n == 2) IP3H |= PRTCH, IP3 &= ~PRTC; \ + if(n == 3) IP3H |= PRTCH, IP3 |= PRTC; \ + }while(0) +#else + +//ÔöÇ¿ÐÍPWM1ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM1_Priority(n) do{if(n == 0) IP3H &= ~PPWM1H, IP3 &= ~PPWM1; \ + if(n == 1) IP3H &= ~PPWM1H, IP3 |= PPWM1; \ + if(n == 2) IP3H |= PPWM1H, IP3 &= ~PPWM1; \ + if(n == 3) IP3H |= PPWM1H, IP3 |= PPWM1; \ + }while(0) +//ÔöÇ¿ÐÍPWM2ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM2_Priority(n) do{if(n == 0) IP3H &= ~PPWM2H, IP3 &= ~PPWM2; \ + if(n == 1) IP3H &= ~PPWM2H, IP3 |= PPWM2; \ + if(n == 2) IP3H |= PPWM2H, IP3 &= ~PPWM2; \ + if(n == 3) IP3H |= PPWM2H, IP3 |= PPWM2; \ + }while(0) + +#endif + +//ÔöÇ¿ÐÍPWM3ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM3_Priority(n) do{if(n == 0) IP3H &= ~PPWM3H, IP3 &= ~PPWM3; \ + if(n == 1) IP3H &= ~PPWM3H, IP3 |= PPWM3; \ + if(n == 2) IP3H |= PPWM3H, IP3 &= ~PPWM3; \ + if(n == 3) IP3H |= PPWM3H, IP3 |= PPWM3; \ + }while(0) +//ÔöÇ¿ÐÍPWM4ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM4_Priority(n) do{if(n == 0) IP3H &= ~PPWM4H, IP3 &= ~PPWM4; \ + if(n == 1) IP3H &= ~PPWM4H, IP3 |= PPWM4; \ + if(n == 2) IP3H |= PPWM4H, IP3 &= ~PPWM4; \ + if(n == 3) IP3H |= PPWM4H, IP3 |= PPWM4; \ + }while(0) +//ÔöÇ¿ÐÍPWM5ÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM5_Priority(n) do{if(n == 0) IP3H &= ~PPWM5H, IP3 &= ~PPWM5; \ + if(n == 1) IP3H &= ~PPWM5H, IP3 |= PPWM5; \ + if(n == 2) IP3H |= PPWM5H, IP3 &= ~PPWM5; \ + if(n == 3) IP3H |= PPWM5H, IP3 |= PPWM5; \ + }while(0) +//ÔöÇ¿ÐÍPWM4Òì³£¼ì²âÖжÏÓÅÏȼ¶¿ØÖÆ +#define PWM4FD_Priority(n) do{if(n == 0) IP3H &= ~PPWM4FDH, IP3 &= ~PPWM4FD; \ + if(n == 1) IP3H &= ~PPWM4FDH, IP3 |= PPWM4FD; \ + if(n == 2) IP3H |= PPWM4FDH, IP3 &= ~PPWM4FD; \ + if(n == 3) IP3H |= PPWM4FDH, IP3 |= PPWM4FD; \ + }while(0) +//´®¿Ú3ÖжÏÓÅÏȼ¶¿ØÖÆ +#define UART3_Priority(n) do{if(n == 0) IP3H &= ~PS3H, IP3 &= ~PS3; \ + if(n == 1) IP3H &= ~PS3H, IP3 |= PS3; \ + if(n == 2) IP3H |= PS3H, IP3 &= ~PS3; \ + if(n == 3) IP3H |= PS3H, IP3 |= PS3; \ + }while(0) +//´®¿Ú4ÖжÏÓÅÏȼ¶¿ØÖÆ +#define UART4_Priority(n) do{if(n == 0) IP3H &= ~PS4H, IP3 &= ~PS4; \ + if(n == 1) IP3H &= ~PS4H, IP3 |= PS4; \ + if(n == 2) IP3H |= PS4H, IP3 &= ~PS4; \ + if(n == 3) IP3H |= PS4H, IP3 |= PS4; \ + }while(0) + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IP = 0xB8; //ÖжÏÓÅÏȼ¶µÍλ PPCA PLVD PADC PS PT1 PX1 PT0 PX0 0000,0000 +//-------- +sbit PPCA = IP^7; //PCA Ä£¿éÖжÏÓÅÏȼ¶ +sbit PLVD = IP^6; //µÍѹ¼à²âÖжÏÓÅÏȼ¶ +sbit PADC = IP^5; //ADC ÖжÏÓÅÏȼ¶ +sbit PS = IP^4; //´®ÐÐÖжÏ0ÓÅÏȼ¶É趨λ +sbit PT1 = IP^3; //¶¨Ê±ÖжÏ1ÓÅÏȼ¶É趨λ +sbit PX1 = IP^2; //ÍⲿÖжÏ1ÓÅÏȼ¶É趨λ +sbit PT0 = IP^1; //¶¨Ê±ÖжÏ0ÓÅÏȼ¶É趨λ +sbit PX0 = IP^0; //ÍⲿÖжÏ0ÓÅÏȼ¶É趨λ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IPH = 0xB7; //ÖжÏÓÅÏȼ¶¸ßλ PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H 0000,0000 +#define PPCAH 0x80 +#define PLVDH 0x40 +#define PADCH 0x20 +#define PSH 0x10 +#define PT1H 0x08 +#define PX1H 0x04 +#define PT0H 0x02 +#define PX0H 0x01 + +//ÍⲿÖжÏ0ÖжÏÓÅÏȼ¶¿ØÖÆ +#define INT0_Priority(n) do{if(n == 0) IPH &= ~PX0H, PX0 = 0; \ + if(n == 1) IPH &= ~PX0H, PX0 = 1; \ + if(n == 2) IPH |= PX0H, PX0 = 0; \ + if(n == 3) IPH |= PX0H, PX0 = 1; \ + }while(0) +//ÍⲿÖжÏ1ÖжÏÓÅÏȼ¶¿ØÖÆ +#define INT1_Priority(n) do{if(n == 0) IPH &= ~PX1H, PX1 = 0; \ + if(n == 1) IPH &= ~PX1H, PX1 = 1; \ + if(n == 2) IPH |= PX1H, PX1 = 0; \ + if(n == 3) IPH |= PX1H, PX1 = 1; \ + }while(0) +//¶¨Ê±Æ÷0ÖжÏÓÅÏȼ¶¿ØÖÆ +#define Timer0_Priority(n) do{if(n == 0) IPH &= ~PT0H, PT0 = 0; \ + if(n == 1) IPH &= ~PT0H, PT0 = 1; \ + if(n == 2) IPH |= PT0H, PT0 = 0; \ + if(n == 3) IPH |= PT0H, PT0 = 1; \ + }while(0) +//¶¨Ê±Æ÷1ÖжÏÓÅÏȼ¶¿ØÖÆ +#define Timer1_Priority(n) do{if(n == 0) IPH &= ~PT1H, PT1 = 0; \ + if(n == 1) IPH &= ~PT1H, PT1 = 1; \ + if(n == 2) IPH |= PT1H, PT1 = 0; \ + if(n == 3) IPH |= PT1H, PT1 = 1; \ + }while(0) +//´®¿Ú1ÖжÏÓÅÏȼ¶¿ØÖÆ +#define UART1_Priority(n) do{if(n == 0) IPH &= ~PSH, PS = 0; \ + if(n == 1) IPH &= ~PSH, PS = 1; \ + if(n == 2) IPH |= PSH, PS = 0; \ + if(n == 3) IPH |= PSH, PS = 1; \ + }while(0) +//ADCÖжÏÓÅÏȼ¶¿ØÖÆ +#define ADC_Priority(n) do{if(n == 0) IPH &= ~PADCH, PADC = 0; \ + if(n == 1) IPH &= ~PADCH, PADC = 1; \ + if(n == 2) IPH |= PADCH, PADC = 0; \ + if(n == 3) IPH |= PADCH, PADC = 1; \ + }while(0) +//µÍѹ¼ì²âÖжÏÓÅÏȼ¶¿ØÖÆ +#define LVD_Priority(n) do{if(n == 0) IPH &= ~PLVDH, PADC = 0; \ + if(n == 1) IPH &= ~PLVDH, PADC = 1; \ + if(n == 2) IPH |= PLVDH, PADC = 0; \ + if(n == 3) IPH |= PLVDH, PADC = 1; \ + }while(0) +//CCP/PCA/PWMÖжÏÓÅÏȼ¶¿ØÖÆ +#define PCA_Priority(n) do{if(n == 0) IPH &= ~PPCAH, PPCA = 0; \ + if(n == 1) IPH &= ~PPCAH, PPCA = 1; \ + if(n == 2) IPH |= PPCAH, PPCA = 0; \ + if(n == 3) IPH |= PPCAH, PPCA = 1; \ + }while(0) + +//#define PCA_InterruptFirst() PPCA = 1 +//#define LVD_InterruptFirst() PLVD = 1 +//#define ADC_InterruptFirst() PADC = 1 +//#define UART1_InterruptFirst() PS = 1 +//#define Timer1_InterruptFirst() PT1 = 1 +//#define INT1_InterruptFirst() PX1 = 1 +//#define Timer0_InterruptFirst() PT0 = 1 +//#define INT0_InterruptFirst() PX0 = 1 + + +/*************************************************************************************************/ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CMPCR1 = 0xE6; CMPEN CMPIF PIE NIE PIS NIS CMPOE CMPRES 00000000B +#define CMPEN 0x80 //1: ÔÊÐí±È½ÏÆ÷, 0: ½ûÖ¹,¹Ø±Õ±È½ÏÆ÷µçÔ´ +#define CMPIF 0x40 //±È½ÏÆ÷ÖжϱêÖ¾, °üÀ¨ÉÏÉýÑØ»òϽµÑØÖжÏ, Èí¼þÇå0 +#define PIE 0x20 //1: ±È½Ï½á¹ûÓÉ0±ä1, ²úÉúÉÏÉýÑØÖÐ¶Ï +#define NIE 0x10 //1: ±È½Ï½á¹ûÓÉ1±ä0, ²úÉúϽµÑØÖÐ¶Ï +#define PIS 0x08 //ÊäÈëÕý¼«ÐÔÑ¡Ôñ, 0: Ñ¡ÔñÄÚ²¿P3.7×öÕýÊäÈë, 1: ÓÉADC_CHS[3:0]ËùÑ¡ÔñµÄADCÊäÈë¶Ë×öÕýÊäÈë. +#define NIS 0x04 //ÊäÈ븺¼«ÐÔÑ¡Ôñ, 0: Ñ¡ÔñÄÚ²¿BandGapµçѹBGv×ö¸ºÊäÈë, 1: Ñ¡ÔñÍⲿP3.6×öÊäÈë. +#define CMPOE 0x02 //1: ÔÊÐí±È½Ï½á¹ûÊä³ö, 0: ½ûÖ¹. +#define CMPRES 0x01 //±È½Ï½á¹û, 1: CMP+µçƽ¸ßÓÚCMP-, 0: CMP+µçƽµÍÓÚCMP-, Ö»¶Á + +#define CMP_P_P37 0x00 //ÊäÈëÕý¼«ÐÔÑ¡Ôñ, 0: Ñ¡ÔñÄÚ²¿P3.7×öÕýÊäÈë +#define CMP_P_ADC 0x08 //ÊäÈëÕý¼«ÐÔÑ¡Ôñ, 1: ÓÉADC_CHS[3:0]ËùÑ¡ÔñµÄADCÊäÈë¶Ë×öÕýÊäÈë. +#define CMP_N_GAP 0x00 //ÊäÈ븺¼«ÐÔÑ¡Ôñ, 0: Ñ¡ÔñÄÚ²¿BandGapµçѹBGv×ö¸ºÊäÈë. +#define CMP_N_P36 0x04 //ÊäÈ븺¼«ÐÔÑ¡Ôñ, 1: Ñ¡ÔñÍⲿP3.6×öÊäÈë. + +#define CMPO_P34() P_SW2 &= ~0x08 //½á¹ûÊä³öµ½P3.4. +#define CMPO_P41() P_SW2 |= 0x08 //½á¹ûÊä³öµ½P4.1. + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CMPCR2 = 0xE7; INVCMPO DISFLT LCDTY[5:0] 00001001B +#define INVCMPO 0x80 //1: ±È½ÏÆ÷Êä³öIOÈ¡·´, 0: ²»È¡·´ +#define DISFLT 0x40 //1: ¹Ø±Õ0.1uFÂ˲¨, 0: ÔÊÐí +#define LCDTY 0x00 //0~63, ±È½Ï½á¹û±ä»¯ÑÓʱÖÜÆÚÊý + + + +/*************************************************************************************************/ +// 7 6 5 4 3 2 1 0 Reset Value +//sfr SCON = 0x98; SM0 SM1 SM2 REN TB8 RB8 TI RI 00000000B //S1 Control + +#define S1_DoubleRate() PCON |= 0x80 +#define S1_SHIFT() SCON &= 0x3f + +#define S1_8bit() SCON = (SCON & 0x3f) | 0x40 +#define S1_9bit() SCON = (SCON & 0x3f) | 0xc0 +#define S1_RX_Enable() SCON |= 0x10 +#define S1_RX_Disable() SCON &= ~0x10 +#define TI1 TI /* ÅжÏTI1ÊÇ·ñ·¢ËÍÍê³É */ +#define RI1 RI /* ÅжÏRI1ÊÇ·ñ½ÓÊÕÍê³É */ +#define SET_TI1() TI = 1 /* ÉèÖÃTI1(ÒýÆðÖжÏ) */ +#define CLR_TI1() TI = 0 /* Çå³ýTI1 */ +#define CLR_RI1() RI = 0 /* Çå³ýRI1 */ +#define S1TB8_SET() TB8 = 1 /* ÉèÖÃTB8 */ +#define S1TB8_CLR() TB8 = 0 /* Çå³ýTB8 */ +#define S1_Int_Enable() ES = 1 /* ´®¿Ú1ÔÊÐíÖÐ¶Ï */ +#define S1_Int_Disable() ES = 0 /* ´®¿Ú1½ûÖ¹ÖÐ¶Ï */ +#define S1_BRT_UseTimer1() AUXR &= ~1 +#define S1_BRT_UseTimer2() AUXR |= 1 +#define S1_USE_P30P31() P_SW1 &= ~0xc0 //UART1 ʹÓÃP30 P31¿Ú ĬÈÏ +#define S1_USE_P36P37() P_SW1 = (P_SW1 & ~0xc0) | 0x40 //UART1 ʹÓÃP36 P37¿Ú +#define S1_USE_P16P17() P_SW1 = (P_SW1 & ~0xc0) | 0x80 //UART1 ʹÓÃP16 P17¿Ú +#define S1_USE_P43P44() P_SW1 |= 0xc0 //UART1 ʹÓÃP43 P44¿Ú +//#define S1_TXD_RXD_SHORT() PCON2 |= (1<<4) //½«TXDÓëRXDÁ¬½ÓÖмÌÊä³ö +//#define S1_TXD_RXD_OPEN() PCON2 &= ~(1<<4) //½«TXDÓëRXDÁ¬½ÓÖм̶Ͽª ĬÈÏ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr S2CON = 0x9A; S2SM0 - S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B //S2 Control + +#define S2_MODE0() S2CON &= ~(1<<7) /* ´®¿Ú2ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */ +#define S2_MODE1() S2CON |= (1<<7) /* ´®¿Ú2ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */ +#define S2_8bit() S2CON &= ~(1<<7) /* ´®¿Ú2ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */ +#define S2_9bit() S2CON |= (1<<7) /* ´®¿Ú2ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */ +#define S2_RX_Enable() S2CON |= (1<<4) /* ÔÊÐí´®2½ÓÊÕ */ +#define S2_RX_Disable() S2CON &= ~(1<<4) /* ½ûÖ¹´®2½ÓÊÕ */ +#define TI2 (S2CON & 2) /* ÅжÏTI2ÊÇ·ñ·¢ËÍÍê³É */ +#define RI2 (S2CON & 1) /* ÅжÏRI2ÊÇ·ñ½ÓÊÕÍê³É */ +#define SET_TI2() S2CON |= (1<<1) /* ÉèÖÃTI2(ÒýÆðÖжÏ) */ +#define CLR_TI2() S2CON &= ~(1<<1) /* Çå³ýTI2 */ +#define CLR_RI2() S2CON &= ~1 /* Çå³ýRI2 */ +#define S2TB8_SET() S2CON |= (1<<3) /* ÉèÖÃTB8 */ +#define S2TB8_CLR() S2CON &= ~(1<<3) /* Çå³ýTB8 */ +#define S2_Int_Enable() IE2 |= 1 /* ´®¿Ú2ÔÊÐíÖÐ¶Ï */ +#define S2_Int_Disable() IE2 &= ~1 /* ´®¿Ú2½ûÖ¹ÖÐ¶Ï */ +#define S2_USE_P10P11() P_SW2 &= ~1 /* UART2 ʹÓÃP1¿Ú ĬÈÏ */ +#define S2_USE_P46P47() P_SW2 |= 1 /* UART2 ʹÓÃP4¿Ú */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr S3CON = 0xAC; S3SM0 S3ST3 S3SM2 S3REN S3TB8 S3RB8 S3TI S3RI 00000000B //S3 Control + +#define S3_MODE0() S3CON &= ~(1<<7) /* ´®¿Ú3ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S3_MODE1() S3CON |= (1<<7) /* ´®¿Ú3ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S3_8bit() S3CON &= ~(1<<7) /* ´®¿Ú3ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S3_9bit() S3CON |= (1<<7) /* ´®¿Ú3ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S3_RX_Enable() S3CON |= (1<<4) /* ÔÊÐí´®3½ÓÊÕ */ +#define S3_RX_Disable() S3CON &= ~(1<<4) /* ½ûÖ¹´®3½ÓÊÕ */ +#define TI3 (S3CON & 2) != 0 /* ÅжÏTI3ÊÇ·ñ·¢ËÍÍê³É */ +#define RI3 (S3CON & 1) != 0 /* ÅжÏRI3ÊÇ·ñ½ÓÊÕÍê³É */ +#define SET_TI3() S3CON |= (1<<1) /* ÉèÖÃTI3(ÒýÆðÖжÏ) */ +#define CLR_TI3() S3CON &= ~(1<<1) /* Çå³ýTI3 */ +#define CLR_RI3() S3CON &= ~1 /* Çå³ýRI3 */ +#define S3TB8_SET() S3CON |= (1<<3) /* ÉèÖÃTB8 */ +#define S3TB8_CLR() S3CON &= ~(1<<3) /* Çå³ýTB8 */ +#define S3_Int_Enable() IE2 |= (1<<3) /* ´®¿Ú3ÔÊÐíÖÐ¶Ï */ +#define S3_Int_Disable() IE2 &= ~(1<<3) /* ´®¿Ú3½ûÖ¹ÖÐ¶Ï */ +#define S3_BRT_UseTimer3() S3CON |= (1<<6) /* BRT select Timer3 */ +#define S3_BRT_UseTimer2() S3CON &= ~(1<<6) /* BRT select Timer2 */ +#define S3_USE_P00P01() P_SW2 &= ~2 /* UART3 ʹÓÃP0¿Ú ĬÈÏ */ +#define S3_USE_P50P51() P_SW2 |= 2 /* UART3 ʹÓÃP5¿Ú */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr S4CON = 0x84; S4SM0 S4ST4 S4SM2 S4REN S4TB8 S4RB8 S4TI S4RI 00000000B //S4 Control + +#define S4_MODE0() S4CON &= ~(1<<7) /* ´®¿Ú4ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S4_MODE1() S4CON |= (1<<7) /* ´®¿Ú4ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S4_8bit() S4CON &= ~(1<<7) /* ´®¿Ú4ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S4_9bit() S4CON |= (1<<7) /* ´®¿Ú4ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4 */ +#define S4_RX_Enable() S4CON |= (1<<4) /* ÔÊÐí´®4½ÓÊÕ */ +#define S4_RX_Disable() S4CON &= ~(1<<4) /* ½ûÖ¹´®4½ÓÊÕ */ +#define TI4 (S4CON & 2) != 0 /* ÅжÏTI3ÊÇ·ñ·¢ËÍÍê³É */ +#define RI4 (S4CON & 1) != 0 /* ÅжÏRI3ÊÇ·ñ½ÓÊÕÍê³É */ +#define SET_TI4() S4CON |= 2 /* ÉèÖÃTI3(ÒýÆðÖжÏ) */ +#define CLR_TI4() S4CON &= ~2 /* Çå³ýTI3 */ +#define CLR_RI4() S4CON &= ~1 /* Çå³ýRI3 */ +#define S4TB8_SET() S4CON |= 8 /* ÉèÖÃTB8 */ +#define S4TB8_CLR() S4CON &= ~8 /* Çå³ýTB8 */ +#define S4_Int_Enable() IE2 |= (1<<4) /* ´®¿Ú4ÔÊÐíÖÐ¶Ï */ +#define S4_Int_Disable() IE2 &= ~(1<<4) /* ´®¿Ú4½ûÖ¹ÖÐ¶Ï */ +#define S4_BRT_UseTimer4() S4CON |= (1<<6) /* BRT select Timer4 */ +#define S4_BRT_UseTimer2() S4CON &= ~(1<<6) /* BRT select Timer2 */ +#define S4_USE_P02P03() P_SW2 &= ~4 /* UART4 ʹÓÃP0¿Ú ĬÈÏ */ +#define S4_USE_P52P53() P_SW2 |= 4 /* UART4 ʹÓÃP5¿Ú */ + + + +/**********************************************************/ +// 7 6 5 4 3 2 1 0 Reset Value +//sfr AUXR = 0x8E; T0x12 T1x12 UART_M0x6 T2R T2_C/T T2x12 EXTRAM S1ST2 0000,0000 //Auxiliary Register + +#define InternalXdata_Disable() AUXR |= 2 /* ½ûֹʹÓÃÄÚ²¿xdata, ËùÓзÃÎÊxdata¶¼ÊÇ·ÃÎÊÍⲿxdata */ +#define InternalXdata_Enable() AUXR &= ~2 /* ÔÊÐíʹÓÃÄÚ²¿xdata, µ±·ÃÎʵĵØÖ·ÔÚÄÚ²¿xdata·¶Î§Ê±, ·ÃÎÊÄÚ²¿µÄxadta, µ±µØÖ·³¬¹ýÄÚ²¿xdataʱ, ·ÃÎÊÍⲿxdata */ +#define S1_M0x6() AUXR |= (1<<5) /* UART Mode0 Speed is 6x Standard */ +#define S1_M0x1() AUXR &= ~(1<<5) /* default, UART Mode0 Speed is Standard */ + +//==================================== +#define Timer0_16bitAutoReload() TMOD &= ~0x03 /* 16λ×Ô¶¯ÖØ×° */ +#define Timer0_16bit() TMOD = (TMOD & ~0x03) | 0x01 /* 16λ */ +#define Timer0_8bitAutoReload() TMOD = (TMOD & ~0x03) | 0x02 /* 8λ×Ô¶¯ÖØ×° */ +#define Timer0_16bitAutoRL_NoMask() TMOD |= 0x03 /* 16λ×Ô¶¯ÖØ×°²»¿ÉÆÁ±ÎÖÐ¶Ï */ +#define Timer0_Run() TR0 = 1 /* ÔÊÐí¶¨Ê±Æ÷0¼ÆÊý */ +#define Timer0_Stop() TR0 = 0 /* ½ûÖ¹¶¨Ê±Æ÷0¼ÆÊý */ +#define Timer0_Gate_INT0_P32() TMOD |= (1<<3) /* ʱÆ÷0ÓÉÍⲿINT0¸ßµçƽÔÊÐí¶¨Ê±¼ÆÊý */ +#define Timer0_AsTimer() TMOD &= ~(1<<2) /* ʱÆ÷0ÓÃ×ö¶¨Ê±Æ÷ */ +#define Timer0_AsCounter() TMOD |= (1<<2) /* ʱÆ÷0ÓÃ×ö¼ÆÊýÆ÷ */ +#define Timer0_AsCounterP34() TMOD |= (1<<2) /* ʱÆ÷0ÓÃ×ö¼ÆÊýÆ÷ */ +#define Timer0_1T() AUXR |= (1<<7) /* Timer0 clodk = fo */ +#define Timer0_12T() AUXR &= ~(1<<7) /* Timer0 clodk = fo/12 12·ÖƵ, default */ +#define Timer0_CLKO_Enable() INT_CLKO |= 1 /* ÔÊÐí T0 Òç³öÂö³åÔÚT0(P3.5)½ÅÊä³ö£¬Fck0 = 1/2 T0 Òç³öÂÊ£¬T0¿ÉÒÔ1T»ò12T¡£ */ +#define Timer0_CLKO_Disable() INT_CLKO &= ~1 +#define Timer0_CLKO_Enable_P34() INT_CLKO |= 1 /* ÔÊÐí T0 Òç³öÂö³åÔÚT0(P3.5)½ÅÊä³ö£¬Fck0 = 1/2 T0 Òç³öÂÊ£¬T0¿ÉÒÔ1T»ò12T¡£ */ +#define Timer0_CLKO_Disable_P34() INT_CLKO &= ~1 +#define Timer0_InterruptEnable() ET0 = 1 /* ÔÊÐíTimer1ÖжÏ.*/ +#define Timer0_InterruptDisable() ET0 = 0 /* ½ûÖ¹Timer1ÖжÏ.*/ + +#define T0_Load(n) TH0 = (n) / 256, TL0 = (n) % 256 +#define T0_Load_us_1T(n) Timer0_AsTimer(),Timer0_1T(), Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/1000)*(n))/1000)/256, TL0=(65536-((MAIN_Fosc/1000)*(n))/1000)%256 +#define T0_Load_us_12T(n) Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/12000)*(n))/1000)/256,TL0=(65536-((MAIN_Fosc/12000)*(n))/1000)%256 +#define T0_Frequency_1T_P35(n) ET0=0,Timer0_AsTimer(),Timer0_1T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit0,TR0=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T0_Frequency_12T_P35(n) ET0=0,Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit0,TR0=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer1_16bitAutoReload() TMOD &= ~0x30 /* 16λ×Ô¶¯ÖØ×° */ +#define Timer1_16bit() TMOD = (TMOD & ~0x30) | 0x10 /* 16λ */ +#define Timer1_8bitAutoReload() TMOD = (TMOD & ~0x30) | 0x20 /* 8λ×Ô¶¯ÖØ×° */ +#define Timer1_Run() TR1 = 1 /* ÔÊÐí¶¨Ê±Æ÷1¼ÆÊý */ +#define Timer1_Stop() TR1 = 0 /* ½ûÖ¹¶¨Ê±Æ÷1¼ÆÊý */ +#define Timer1_Gate_INT1_P33() TMOD |= (1<<7) /* ʱÆ÷1ÓÉÍⲿINT1¸ßµçƽÔÊÐí¶¨Ê±¼ÆÊý */ +#define Timer1_AsTimer() TMOD &= ~(1<<6) /* ʱÆ÷1ÓÃ×ö¶¨Ê±Æ÷ */ +#define Timer1_AsCounter() TMOD |= (1<<6) /* ʱÆ÷1ÓÃ×ö¼ÆÊýÆ÷ */ +#define Timer1_AsCounterP35() TMOD |= (1<<6) /* ʱÆ÷1ÓÃ×ö¼ÆÊýÆ÷ */ +#define Timer1_1T() AUXR |= (1<<6) /* Timer1 clodk = fo */ +#define Timer1_12T() AUXR &= ~(1<<6) /* Timer1 clodk = fo/12 12·ÖƵ, default */ +#define Timer1_CLKO_Enable() INT_CLKO |= 2 /* ÔÊÐí T1 Òç³öÂö³åÔÚT1(P3.4)½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ£¬T1¿ÉÒÔ1T»ò12T¡£ */ +#define Timer1_CLKO_Disable() INT_CLKO &= ~2 +#define Timer1_CLKO_Enable_P35() INT_CLKO |= 2 /* ÔÊÐí T1 Òç³öÂö³åÔÚT1(P3.4)½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ£¬T1¿ÉÒÔ1T»ò12T¡£ */ +#define Timer1_CLKO_Disable_P35() INT_CLKO &= ~2 +#define Timer1_InterruptEnable() ET1 = 1 /* ÔÊÐíTimer1ÖжÏ. */ +#define Timer1_InterruptDisable() ET1 = 0 /* ½ûÖ¹Timer1ÖжÏ. */ + +#define T1_Load(n) TH1 = (n) / 256, TL1 = (n) % 256 +#define T1_Load_us_1T(n) Timer1_AsTimer(),Timer1_1T(), Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T1_Load_us_12T(n) Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T1_Frequency_1T_P34(n) ET1=0,Timer1_AsTimer(),Timer1_1T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit1,TR1=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T1_Frequency_12T_P34(n) ET1=0,Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit1,TR1=1 /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer2_Run() AUXR |= (1<<4) /* ÔÊÐí¶¨Ê±Æ÷2¼ÆÊý */ +#define Timer2_Stop() AUXR &= ~(1<<4) /* ½ûÖ¹¶¨Ê±Æ÷2¼ÆÊý */ +#define Timer2_AsTimer() AUXR &= ~(1<<3) /* ʱÆ÷2ÓÃ×ö¶¨Ê±Æ÷ */ +#define Timer2_AsCounter() AUXR |= (1<<3) /* ʱÆ÷2ÓÃ×ö¼ÆÊýÆ÷ */ +#define Timer2_AsCounterP31() AUXR |= (1<<3) /* ʱÆ÷2ÓÃ×ö¼ÆÊýÆ÷ */ +#define Timer2_1T() AUXR |= (1<<2) /* Timer0 clock = fo */ +#define Timer2_12T() AUXR &= ~(1<<2) /* Timer0 clock = fo/12 12·ÖƵ, default */ +#define Timer2_CLKO_Enable() INT_CLKO |= 4 /* ÔÊÐí T2 Òç³öÂö³åÔÚP1.3½ÅÊä³ö£¬Fck2 = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£ */ +#define Timer2_CLKO_Disable() INT_CLKO &= ~4 +#define Timer2_CLKO_Enable_P13() INT_CLKO |= 4 /* ÔÊÐí T2 Òç³öÂö³åÔÚP1.3½ÅÊä³ö£¬Fck2 = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£ */ +#define Timer2_CLKO_Disable_P13() INT_CLKO &= ~4 +#define Timer2_InterruptEnable() IE2 |= (1<<2) /* ÔÊÐíTimer2ÖжÏ. */ +#define Timer2_InterruptDisable() IE2 &= ~(1<<2) /* ½ûÖ¹Timer2ÖжÏ. */ + +#define T2_Load(n) TH2 = (n) / 256, TL2 = (n) % 256 +#define T2_Load_us_1T(n) Timer2_AsTimer(),Timer2_1T(), TH2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T2_Load_us_12T(n) Timer2_AsTimer(),Timer2_12T(),TH2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T2_Frequency_1T_P30(n) Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_1T(), TH2=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL2=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer2_CLKO_Enable_P30(),Timer2_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T2_Frequency_12T_P30(n) Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_12T(),TH2=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL2=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer2_CLKO_Enable_P30(),Timer2_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer3_Run() T4T3M |= (1<<3) /* ÔÊÐí¶¨Ê±Æ÷3¼ÆÊý */ +#define Timer3_Stop() T4T3M &= ~(1<<3) /* ½ûÖ¹¶¨Ê±Æ÷3¼ÆÊý */ +#define Timer3_AsTimer() T4T3M &= ~(1<<2) /* ʱÆ÷3ÓÃ×ö¶¨Ê±Æ÷ */ +#define Timer3_AsCounter() T4T3M |= (1<<2) /* ʱÆ÷3ÓÃ×ö¼ÆÊýÆ÷, P0.5ΪÍⲿÂö³å */ +#define Timer3_AsCounterP05() T4T3M |= (1<<2) /* ʱÆ÷3ÓÃ×ö¼ÆÊýÆ÷, P0.5ΪÍⲿÂö³å */ +#define Timer3_1T() T4T3M |= (1<<1) /* 1Tģʽ */ +#define Timer3_12T() T4T3M &= ~(1<<1) /* 12Tģʽ, default */ +#define Timer3_CLKO_Enable() T4T3M |= 1 /* ÔÊÐíT3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£ */ +#define Timer3_CLKO_Disable() T4T3M &= ~1 /* ½ûÖ¹T3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö */ +#define Timer3_CLKO_Enable_P04() T4T3M |= 1 /* ÔÊÐíT3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£ */ +#define Timer3_CLKO_Disable_P04() T4T3M &= ~1 /* ½ûÖ¹T3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö */ +#define Timer3_InterruptEnable() IE2 |= (1<<5) /* ÔÊÐíTimer3ÖжÏ. */ +#define Timer3_InterruptDisable() IE2 &= ~(1<<5) /* ½ûÖ¹Timer3ÖжÏ. */ + +#define T3_Load(n) TH3 = (n) / 256, TL3 = (n) % 256 +#define T3_Load_us_1T(n) Timer3_AsTimer(),Timer3_1T(), TH3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T3_Load_us_12T(n) Timer3_AsTimer(),Timer3_12T(),TH3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T3_Frequency_1T_P04(n) Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_1T(), TH3=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL3=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer3_CLKO_P04_Enable,Timer3_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T3_Frequency_12T_P04(n) Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_12T(),TH3=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL3=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer3_CLKO_P04_Enable,Timer3_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ + +//==================================== +#define Timer4_Run() T4T3M |= (1<<7) /* ÔÊÐí¶¨Ê±Æ÷4¼ÆÊý */ +#define Timer4_Stop() T4T3M &= ~(1<<7) /* ½ûÖ¹¶¨Ê±Æ÷4¼ÆÊý */ +#define Timer4_AsTimer() T4T3M &= ~(1<<6) /* ʱÆ÷4ÓÃ×ö¶¨Ê±Æ÷ */ +#define Timer4_AsCounter() T4T3M |= (1<<6) /* ʱÆ÷4ÓÃ×ö¼ÆÊýÆ÷, P0.7ΪÍⲿÂö³å */ +#define Timer4_AsCounterP07() T4T3M |= (1<<6) /* ʱÆ÷4ÓÃ×ö¼ÆÊýÆ÷, P0.7ΪÍⲿÂö³å */ +#define Timer4_1T() T4T3M |= (1<<5) /* 1Tģʽ */ +#define Timer4_12T() T4T3M &= ~(1<<5) /* 12Tģʽ, default */ +#define Timer4_CLKO_Enable() T4T3M |= (1<<4) /* ÔÊÐíT4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£ */ +#define Timer4_CLKO_Disable() T4T3M &= ~(1<<4) /* ½ûÖ¹T4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö */ +#define Timer4_CLKO_Enable_P06() T4T3M |= (1<<4) /* ÔÊÐíT4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£ */ +#define Timer4_CLKO_Disable_P06() T4T3M &= ~(1<<4) /* ½ûÖ¹T4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö */ +#define Timer4_InterruptEnable() IE2 |= (1<<6) /* ÔÊÐíTimer4ÖжÏ. */ +#define Timer4_InterruptDisable() IE2 &= ~(1<<6) /* ½ûÖ¹Timer4ÖжÏ. */ + +#define T4_Load(n) TH4 = (n) / 256, TL4 = (n) % 256 +#define T4_Load_us_1T(n) Timer4_AsTimer(),Timer4_1T(), TH4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256 +#define T4_Load_us_12T(n) Timer4_AsTimer(),Timer4_12T(),TH4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256 +#define T4_Frequency_1T_P06(n) Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_1T(), TH4=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL4=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer4_CLKO_P06_Enable(),Timer4_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +#define T4_Frequency_12T_P06(n) Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_12T(),TH4=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL4=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer4_CLKO_P06_Enable(),Timer4_Run() /* fx=fosc/(2*M)/n, M=1 or M=12 */ +//==================================================================================================================== + +//sfr WDT_CONTR = 0xC1; //Watch-Dog-Timer Control register +// 7 6 5 4 3 2 1 0 Reset Value +// WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0 xx00,0000 +#define D_WDT_FLAG (1<<7) +#define D_EN_WDT (1<<5) +#define D_CLR_WDT (1<<4) /* auto clear */ +#define D_IDLE_WDT (1<<3) /* WDT counter when Idle */ +#define D_WDT_SCALE_2 0 +#define D_WDT_SCALE_4 1 +#define D_WDT_SCALE_8 2 /* T=393216*N/fo */ +#define D_WDT_SCALE_16 3 +#define D_WDT_SCALE_32 4 +#define D_WDT_SCALE_64 5 +#define D_WDT_SCALE_128 6 +#define D_WDT_SCALE_256 7 + +#define WDT_PS_Set(n) WDT_CONTR = (WDT_CONTR & ~0x07) | (n & 0x07) /* ¿´ÃŹ·¶¨Ê±Æ÷ʱÖÓ·ÖƵϵÊýÉèÖà */ +#define WDT_reset(n) WDT_CONTR = D_EN_WDT + D_CLR_WDT + D_IDLE_WDT + (n) /* ³õʼ»¯WDT£¬Î¹¹· */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PCON = 0x87; SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0001,0000 //Power Control +//SMOD //´®¿ÚË«±¶ËÙ +//SMOD0 +#define LVDF (1<<5) /* P4.6µÍѹ¼ì²â±êÖ¾ */ +//POF +//GF1 +//GF0 +//#define D_PD 2 /* set 1, power down mode */ +//#define D_IDLE 1 /* set 1, idle mode */ +#define MCU_IDLE() PCON |= 1 /* MCU ½øÈë IDLE ģʽ */ +#define MCU_POWER_DOWN() PCON |= 2 /* MCU ½øÈë ˯Ãß Ä£Ê½ */ + + +//sfr IAP_CMD = 0xC5; +#define IAP_STANDBY() IAP_CMD = 0 //IAP¿ÕÏÐÃüÁ½ûÖ¹£© +#define IAP_READ() IAP_CMD = 1 //IAP¶Á³öÃüÁî +#define IAP_WRITE() IAP_CMD = 2 //IAPдÈëÃüÁî +#define IAP_ERASE() IAP_CMD = 3 //IAP²Á³ýÃüÁî + +//sfr IAP_TRIG = 0xC6; +#define IAP_TRIG() IAP_TRIG = 0x5A, IAP_TRIG = 0xA5 /* IAP´¥·¢ÃüÁî */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr IAP_CONTR = 0xC7; IAPEN SWBS SWRST CFAIL - - - - 0000,x000 //IAP Control Register + +#define IAP_EN (1<<7) +#define IAP_SWBS (1<<6) +#define IAP_SWRST (1<<5) +#define IAP_CMD_FAIL (1<<4) + +#define IAP_ENABLE() IAP_CONTR = IAP_EN; IAP_TPS = MAIN_Fosc / 1000000 +#define IAP_DISABLE() IAP_CONTR = 0; IAP_CMD = 0; IAP_TRIG = 0; IAP_ADDRH = 0xff; IAP_ADDRL = 0xff + + +/* ADC Register */ +// 7 6 5 4 3 2 1 0 Reset Value +//sfr ADC_CONTR = 0xBC; ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000,0000 /* AD ת»»¿ØÖƼĴæÆ÷ */ +//sfr ADC_RES = 0xBD; ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 0000,0000 /* A/D ת»»½á¹û¸ß8λ */ +//sfr ADC_RESL = 0xBE; ADCV.1 ADCV.0 0000,0000 /* A/D ת»»½á¹ûµÍ2λ */ +//sfr ADC_CONTR = 0xBC; //Ö±½ÓÓÃMOV²Ù×÷£¬²»ÒªÓÃÓë»ò + + +//sfr SPCTL = 0xCE; SPI¿ØÖƼĴæÆ÷ +// 7 6 5 4 3 2 1 0 Reset Value +// SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0x00 + +#define SPI_SSIG_None() SPCTL |= (1<<7) /* 1: ºöÂÔSS½Å */ +#define SPI_SSIG_Enable() SPCTL &= ~(1<<7) /* 0: SS½ÅÓÃÓÚ¾ö¶¨Ö÷´Ó»ú */ +#define SPI_Enable() SPCTL |= (1<<6) /* 1: ÔÊÐíSPI */ +#define SPI_Disable() SPCTL &= ~(1<<6) /* 0: ½ûÖ¹SPI */ +#define SPI_LSB_First() SPCTL |= (1<<5) /* 1: LSBÏÈ·¢ */ +#define SPI_MSB_First() SPCTL &= ~(1<<5) /* 0: MSBÏÈ·¢ */ +#define SPI_Master() SPCTL |= (1<<4) /* 1: ÉèΪÖ÷»ú */ +#define SPI_Slave() SPCTL &= ~(1<<4) /* 0: ÉèΪ´Ó»ú */ +#define SPI_SCLK_NormalH() SPCTL |= (1<<3) /* 1: ¿ÕÏÐʱSCLKΪ¸ßµçƽ */ +#define SPI_SCLK_NormalL() SPCTL &= ~(1<<3) /* 0: ¿ÕÏÐʱSCLKΪµÍµçƽ */ +#define SPI_PhaseH() SPCTL |= (1<<2) /* 1: */ +#define SPI_PhaseL() SPCTL &= ~(1<<2) /* 0: */ +#define SPI_Speed(n) SPCTL = (SPCTL & ~3) | (n) /*ÉèÖÃËÙ¶È, 0 -- fosc/4, 1 -- fosc/8, 2 -- fosc/16, 3 -- fosc/32 */ + +//sfr SPDAT = 0xCF; //SPI Data Register 0000,0000 +//sfr SPSTAT = 0xCD; //SPI״̬¼Ä´æÆ÷ +// 7 6 5 4 3 2 1 0 Reset Value +// SPIF WCOL - - - - - - +#define SPIF 0x80 /* SPI´«ÊäÍê³É±êÖ¾¡£Ð´Èë1Çå0¡£*/ +#define WCOL 0x40 /* SPIд³åÍ»±êÖ¾¡£Ð´Èë1Çå0¡£ */ + +#define SPI_USE_P12P13P14P15() P_SW1 &= ~0x0c /* ½«SPIÇл»µ½P12(SS) P13(MOSI) P14(MISO) P15(SCLK)(ÉϵçĬÈÏ)¡£*/ +#define SPI_USE_P22P23P24P25() P_SW1 = (P_SW1 & ~0x0c) | 0x04 /* ½«SPIÇл»µ½P22(SS) P23(MOSI) P24(MISO) P25(SCLK)¡£*/ +#define SPI_USE_P74P75P76P77() P_SW1 = (P_SW1 & ~0x0c) | 0x08 /* ½«SPIÇл»µ½P74(SS) P75(MOSI) P76(MISO) P77(SCLK)¡£*/ +#define SPI_USE_P35P34P33P32() P_SW1 = P_SW1 | 0x0C /* ½«SPIÇл»µ½P35(SS) P34(MOSI) P33(MISO) P32(SCLK)¡£*/ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CCFG = 0xFE80H; ENI2C MSSL MSSPEED[5:0] 0000,0000 /* I2CÅäÖüĴæÆ÷ */ +#define I2C_Function(n) (n==0?(I2CCFG &= ~0x80):(I2CCFG |= 0x80)) //0£º½ûÖ¹ I2C ¹¦ÄÜ£»1£ºÊ¹ÄÜ I2C ¹¦ÄÜ +#define I2C_ENABLE() I2CCFG |= 0x80 /* ʹÄÜ I2C ¹¦ÄÜ */ +#define I2C_DISABLE() I2CCFG &= ~0x80 /* ½ûÖ¹ I2C ¹¦ÄÜ */ +#define I2C_Master() I2CCFG |= 0x40 /* 1: ÉèΪÖ÷»ú */ +#define I2C_Slave() I2CCFG &= ~0x40 /* 0: ÉèΪ´Ó»ú */ +#define I2C_SetSpeed(n) I2CCFG = (I2CCFG & ~0x3f) | (n & 0x3f) /* ×ÜÏßËÙ¶È=Fosc/2/(Speed*2+4) */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CMSCR = 0xFE81H; EMSI - - - MSCMD[3:0] 0000,0000 /* I2CÅäÖüĴæÆ÷ */ +#define I2C_Master_Inturrupt(n) (n==0?(I2CMSCR &= ~0x80):(I2CMSCR |= 0x80)) //0£º½ûÖ¹ I2C ¹¦ÄÜ£»1£ºÊ¹ÄÜ I2C ¹¦ÄÜ + +#define I2C_CMD_None 0 +#define I2C_CMD_Start 1 +#define I2C_CMD_Send 2 +#define I2C_CMD_RACK 3 +#define I2C_CMD_Read 4 +#define I2C_CMD_SACK 5 +#define I2C_CMD_Stop 6 +#define I2C_CMD_RFU1 7 +#define I2C_CMD_RFU2 8 +#define I2C_CMD_Start_Send_RACK 9 +#define I2C_CMD_Send_RACK 10 +#define I2C_CMD_Read_SACK 11 +#define I2C_CMD_Read_SNAK 12 + +#define I2C_Command(n) I2CMSCR = (I2CMSCR & ~0x0f) | (n & 0x0f) /* Ö÷»úÃüÁî */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CMSST = 0xFE82H; MSBUSY MSIF - - - - MSACKI MSACKO 0000,0000 /* I2CÖ÷»ú״̬¼Ä´æÆ÷ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CMSAUX = 0xFE88H; - - - - - - - WDTA 0000,0000 /* I2CÖ÷»ú¸¨Öú¿ØÖƼĴæÆ÷ */ +#define I2C_WDTA_EN() I2CMSAUX |= 0x01 /* ʹÄÜ×Ô¶¯·¢ËÍ */ +#define I2C_WDTA_DIS() I2CMSAUX &= ~0x01 /* ½ûÖ¹×Ô¶¯·¢ËÍ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CSLCR = 0xFE83H; - ESTAI ERXI ETXI ESTOI - - SLRET 0000,0000 /* I2C´Ó»ú¿ØÖƼĴæÆ÷ */ +#define I2C_ESTAI_EN() I2CSLCR |= 0x40 /* ʹÄÜ´Ó»ú½ÓÊÕSTARTÐźÅÖÐ¶Ï */ +#define I2C_ESTAI_DIS() I2CSLCR &= ~0x40 /* ½ûÖ¹´Ó»ú½ÓÊÕSTARTÐźÅÖÐ¶Ï */ +#define I2C_ERXI_EN() I2CSLCR |= 0x20 /* ʹÄÜ´Ó»ú½ÓÊÕ1×Ö½ÚÊý¾ÝÖÐ¶Ï */ +#define I2C_ERXI_DIS() I2CSLCR &= ~0x20 /* ½ûÖ¹´Ó»ú½ÓÊÕ1×Ö½ÚÊý¾ÝÖÐ¶Ï */ +#define I2C_ETXI_EN() I2CSLCR |= 0x10 /* ʹÄÜ´Ó»ú·¢ËÍ1×Ö½ÚÊý¾ÝÖÐ¶Ï */ +#define I2C_ETXI_DIS() I2CSLCR &= ~0x10 /* ½ûÖ¹´Ó»ú·¢ËÍ1×Ö½ÚÊý¾ÝÖÐ¶Ï */ +#define I2C_ESTOI_EN() I2CSLCR |= 0x08 /* ʹÄÜ´Ó»ú½ÓÊÕSTOPÐźÅÖÐ¶Ï */ +#define I2C_ESTOI_DIS() I2CSLCR &= ~0x08 /* ½ûÖ¹´Ó»ú½ÓÊÕSTOPÐźÅÖÐ¶Ï */ +#define I2C_SLRET() I2CSLCR |= 0x01 /* ¸´Î»´Ó»úģʽ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CSLST = 0xFE84H; SLBUSY STAIF RXIF TXIF STOIF - SLACKI SLACKO 0000,0000 /* I2C´Ó»ú״̬¼Ä´æÆ÷ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr I2CSLADR = 0xFE85H; I2CSLADR[7:1] MA 0000,0000 /* I2C´Ó»úµØÖ·¼Ä´æÆ÷ */ +#define I2C_Address(n) I2CSLADR = (I2CSLADR & 0x01) | (n << 1) /* ´Ó»úµØÖ· */ +#define I2C_MATCH_EN() I2CSLADR &= ~0x01 /* ʹÄÜ´Ó»úµØÖ·±È½Ï¹¦ÄÜ£¬Ö»½ÓÊÜÏàÆ¥ÅäµØÖ· */ +#define I2C_MATCH_DIS() I2CSLADR |= 0x01 /* ½ûÖ¹´Ó»úµØÖ·±È½Ï¹¦ÄÜ£¬½ÓÊÜËùÓÐÉ豸µØÖ· */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_ENO = 0xFEB1H; ENO4N ENO4P ENO3N ENO3P ENO2N ENO2P ENO1N ENO1P 0000,0000 /* Êä³öʹÄܼĴæÆ÷ */ +//sfr PWMB_ENO = 0xFEB5H; - ENO8P - ENO7P - ENO6P - ENO5P 0000,0000 /* Êä³öʹÄܼĴæÆ÷ */ +#define PWM1P_OUT_EN() PWMA_ENO |= 0x01 /* ʹÄÜ PWM1P Êä³ö */ +#define PWM1P_OUT_DIS() PWMA_ENO &= ~0x01 /* ½ûÖ¹ PWM1P Êä³ö */ +#define PWM1N_OUT_EN() PWMA_ENO |= 0x02 /* ʹÄÜ PWM1N Êä³ö */ +#define PWM1N_OUT_DIS() PWMA_ENO &= ~0x02 /* ½ûÖ¹ PWM1N Êä³ö */ +#define PWM2P_OUT_EN() PWMA_ENO |= 0x04 /* ʹÄÜ PWM2P Êä³ö */ +#define PWM2P_OUT_DIS() PWMA_ENO &= ~0x04 /* ½ûÖ¹ PWM2P Êä³ö */ +#define PWM2N_OUT_EN() PWMA_ENO |= 0x08 /* ʹÄÜ PWM2N Êä³ö */ +#define PWM2N_OUT_DIS() PWMA_ENO &= ~0x08 /* ½ûÖ¹ PWM2N Êä³ö */ +#define PWM3P_OUT_EN() PWMA_ENO |= 0x10 /* ʹÄÜ PWM3P Êä³ö */ +#define PWM3P_OUT_DIS() PWMA_ENO &= ~0x10 /* ½ûÖ¹ PWM3P Êä³ö */ +#define PWM3N_OUT_EN() PWMA_ENO |= 0x20 /* ʹÄÜ PWM3N Êä³ö */ +#define PWM3N_OUT_DIS() PWMA_ENO &= ~0x20 /* ½ûÖ¹ PWM3N Êä³ö */ +#define PWM4P_OUT_EN() PWMA_ENO |= 0x40 /* ʹÄÜ PWM3P Êä³ö */ +#define PWM4P_OUT_DIS() PWMA_ENO &= ~0x40 /* ½ûÖ¹ PWM3P Êä³ö */ +#define PWM4N_OUT_EN() PWMA_ENO |= 0x80 /* ʹÄÜ PWM3N Êä³ö */ +#define PWM4N_OUT_DIS() PWMA_ENO &= ~0x80 /* ½ûÖ¹ PWM3N Êä³ö */ + +#define PWM5P_OUT_EN() PWMB_ENO |= 0x01 /* ʹÄÜ PWM5P Êä³ö */ +#define PWM5P_OUT_DIS() PWMB_ENO &= ~0x01 /* ½ûÖ¹ PWM5P Êä³ö */ +#define PWM6P_OUT_EN() PWMB_ENO |= 0x04 /* ʹÄÜ PWM6P Êä³ö */ +#define PWM6P_OUT_DIS() PWMB_ENO &= ~0x04 /* ½ûÖ¹ PWM6P Êä³ö */ +#define PWM7P_OUT_EN() PWMB_ENO |= 0x10 /* ʹÄÜ PWM7P Êä³ö */ +#define PWM7P_OUT_DIS() PWMB_ENO &= ~0x10 /* ½ûÖ¹ PWM7P Êä³ö */ +#define PWM8P_OUT_EN() PWMB_ENO |= 0x40 /* ʹÄÜ PWM8P Êä³ö */ +#define PWM8P_OUT_DIS() PWMB_ENO &= ~0x40 /* ½ûÖ¹ PWM8P Êä³ö */ + +#define PWMA_OutChannelSel(n) PWMA_ENO = n //Ñ¡ÔñÊä³öͨµÀ +#define PWMB_OutChannelSel(n) PWMB_ENO = n //Ñ¡ÔñÊä³öͨµÀ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_PS = 0xFEB2H; C4PS1 C4PS0 C3PS1 C3PS0 C2PS1 C2PS0 C1PS1 C1PS0 0000,0000 /* Êä³öʹÄܼĴæÆ÷ */ +//sfr PWMB_PS = 0xFEB6H; C8PS1 C8PS0 C7PS1 C7PS0 C6PS1 C6PS0 C5PS1 C5PS0 0000,0000 /* Êä³öʹÄܼĴæÆ÷ */ + +#define PWM1_USE_P10P11() PWMA_PS = (PWMA_PS & ~0x03) /* PWM ͨµÀ 1 Êä³ö½ÅÇл»µ½P10(PWM1P) P11(PWM1N) */ +#define PWM1_USE_P20P21() PWMA_PS = (PWMA_PS & ~0x03) | 0x01 /* PWM ͨµÀ 1 Êä³ö½ÅÇл»µ½P20(PWM1P) P21(PWM1N) */ +#define PWM1_USE_P60P61() PWMA_PS = (PWMA_PS & ~0x03) | 0x02 /* PWM ͨµÀ 1 Êä³ö½ÅÇл»µ½P60(PWM1P) P61(PWM1N) */ + +#define PWM2_USE_P12P13() PWMA_PS = (PWMA_PS & ~0x0C) /* PWM ͨµÀ 2 Êä³ö½ÅÇл»µ½P12/P54(PWM2P) P13(PWM2N) */ +#define PWM2_USE_P22P23() PWMA_PS = (PWMA_PS & ~0x0C) | 0x04 /* PWM ͨµÀ 2 Êä³ö½ÅÇл»µ½P22(PWM2P) P23(PWM2N) */ +#define PWM2_USE_P62P63() PWMA_PS = (PWMA_PS & ~0x0C) | 0x08 /* PWM ͨµÀ 2 Êä³ö½ÅÇл»µ½P62(PWM2P) P63(PWM2N) */ + +#define PWM3_USE_P14P15() PWMA_PS = (PWMA_PS & ~0x30) /* PWM ͨµÀ 3 Êä³ö½ÅÇл»µ½P14(PWM3P) P15(PWM3N) */ +#define PWM3_USE_P24P25() PWMA_PS = (PWMA_PS & ~0x30) | 0x10 /* PWM ͨµÀ 3 Êä³ö½ÅÇл»µ½P24(PWM3P) P25(PWM3N) */ +#define PWM3_USE_P64P65() PWMA_PS = (PWMA_PS & ~0x30) | 0x20 /* PWM ͨµÀ 3 Êä³ö½ÅÇл»µ½P64(PWM3P) P65(PWM3N) */ + +#define PWM4_USE_P16P17() PWMA_PS = (PWMA_PS & ~0xC0) /* PWM ͨµÀ 4 Êä³ö½ÅÇл»µ½P16(PWM4P) P17(PWM4N) */ +#define PWM4_USE_P26P27() PWMA_PS = (PWMA_PS & ~0xC0) | 0x40 /* PWM ͨµÀ 4 Êä³ö½ÅÇл»µ½P26(PWM4P) P27(PWM4N) */ +#define PWM4_USE_P66P67() PWMA_PS = (PWMA_PS & ~0xC0) | 0x80 /* PWM ͨµÀ 4 Êä³ö½ÅÇл»µ½P66(PWM4P) P67(PWM4N) */ +#define PWM4_USE_P34P33() PWMA_PS = (PWMA_PS | 0xC0) /* PWM ͨµÀ 4 Êä³ö½ÅÇл»µ½P34(PWM4P) P33(PWM4N) */ + +#define PWM5_USE_P20() PWMB_PS = (PWMB_PS & ~0x03) /* PWM ͨµÀ 5 Êä³ö½ÅÇл»µ½P20(PWM5) */ +#define PWM5_USE_P17() PWMB_PS = (PWMB_PS & ~0x03) | 0x01 /* PWM ͨµÀ 5 Êä³ö½ÅÇл»µ½P17(PWM5) */ +#define PWM5_USE_P00() PWMB_PS = (PWMB_PS & ~0x03) | 0x02 /* PWM ͨµÀ 5 Êä³ö½ÅÇл»µ½P00(PWM5) */ +#define PWM5_USE_P74() PWMB_PS = (PWMB_PS | 0x03) /* PWM ͨµÀ 5 Êä³ö½ÅÇл»µ½P74(PWM5) */ + +#define PWM6_USE_P21() PWMB_PS = (PWMB_PS & ~0x0C) /* PWM ͨµÀ 6 Êä³ö½ÅÇл»µ½P21(PWM6) */ +#define PWM6_USE_P54() PWMB_PS = (PWMB_PS & ~0x0C) | 0x04 /* PWM ͨµÀ 6 Êä³ö½ÅÇл»µ½P54(PWM6) */ +#define PWM6_USE_P01() PWMB_PS = (PWMB_PS & ~0x0C) | 0x08 /* PWM ͨµÀ 6 Êä³ö½ÅÇл»µ½P01(PWM6) */ +#define PWM6_USE_P75() PWMB_PS = (PWMB_PS | 0x0C) /* PWM ͨµÀ 6 Êä³ö½ÅÇл»µ½P75(PWM6) */ + +#define PWM7_USE_P22() PWMB_PS = (PWMB_PS & ~0x30) /* PWM ͨµÀ 7 Êä³ö½ÅÇл»µ½P22(PWM7) */ +#define PWM7_USE_P33() PWMB_PS = (PWMB_PS & ~0x30) | 0x10 /* PWM ͨµÀ 7 Êä³ö½ÅÇл»µ½P33(PWM7) */ +#define PWM7_USE_P02() PWMB_PS = (PWMB_PS & ~0x30) | 0x20 /* PWM ͨµÀ 7 Êä³ö½ÅÇл»µ½P02(PWM7) */ +#define PWM7_USE_P76() PWMB_PS = (PWMB_PS | 0x30) /* PWM ͨµÀ 7 Êä³ö½ÅÇл»µ½P76(PWM7) */ + +#define PWM8_USE_P23() PWMB_PS = (PWMB_PS & ~0xC0) /* PWM ͨµÀ 8 Êä³ö½ÅÇл»µ½P23(PWM8) */ +#define PWM8_USE_P34() PWMB_PS = (PWMB_PS & ~0xC0) | 0x40 /* PWM ͨµÀ 8 Êä³ö½ÅÇл»µ½P34(PWM8) */ +#define PWM8_USE_P03() PWMB_PS = (PWMB_PS & ~0xC0) | 0x80 /* PWM ͨµÀ 8 Êä³ö½ÅÇл»µ½P03(PWM8) */ +#define PWM8_USE_P77() PWMB_PS = (PWMB_PS | 0xC0) /* PWM ͨµÀ 8 Êä³ö½ÅÇл»µ½P77(PWM8) */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_IOAUX = 0xFEB3H; AUX4N AUX4P AUX3N AUX3P AUX2N AUX2P AUX1N AUX1P 0000,0000 /* Êä³ö¸½¼ÓʹÄܼĴæÆ÷ */ +//sfr PWMB_IOAUX = 0xFEB7H; - AUX8P - AUX7P - AUX6P - AUX5P 0000,0000 /* Êä³ö¸½¼ÓʹÄܼĴæÆ÷ */ +#define AUX4N (1<<7) +#define AUX4P (1<<6) +#define AUX3N (1<<5) +#define AUX3P (1<<4) +#define AUX2N (1<<3) +#define AUX2P (1<<2) +#define AUX1N (1<<1) +#define AUX1P (1) + +#define AUX8P (1<<6) +#define AUX7P (1<<4) +#define AUX6P (1<<2) +#define AUX5P (1) + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CR1 = 0xFEC0H; ARPEA CMSA1 CMSA0 DIRA OPMA URSA UDISA CENA 0000,0000 /* ¿ØÖƼĴæÆ÷ 1 */ +//sfr PWMB_CR1 = 0xFEE0H; ARPEB CMSB1 CMSB0 DIRB OPMB URSB UDISB CENB 0000,0000 /* ¿ØÖƼĴæÆ÷ 1 */ +#define ARPE1 (1<<7) +#define ARPE2 (1<<7) +#define PWMA_AlignMode_Edge() PWMA_CR1 = (PWMA_CR1 & ~0x60) +#define PWMA_AlignMode_Mid1() PWMA_CR1 = (PWMA_CR1 & ~0x60) | 0x20 +#define PWMA_AlignMode_Mid2() PWMA_CR1 = (PWMA_CR1 & ~0x60) | 0x40 +#define PWMA_AlignMode_Mid3() PWMA_CR1 = (PWMA_CR1 | 0x60) +#define PWMA_DIR_UP() PWMA_CR1 &= ~0x10 +#define PWMA_DIR_DN() PWMA_CR1 |= 0x10 +#define PWMA_OPMA(n) (n==0?(PWMA_CR1 &= ~0x08):(PWMA_CR1 |= 0x08)) //µ¥Âö³åģʽ 0£ºÔÚ·¢Éú¸üÐÂʼþʱ£¬¼ÆÊýÆ÷²»Í£Ö¹£»1£ºÔÚ·¢ÉúÏÂÒ»´Î¸üÐÂʼþʱ£¬Çå³ý CEN 룬¼ÆÊýÆ÷Í£Ö¹ +#define PWMA_URSA(n) (n==0?(PWMA_CR1 &= ~0x04):(PWMA_CR1 |= 0x04)) //¸üÐÂÇëÇóÔ´ +#define PWMA_UDISA(n) (n==0?(PWMA_CR1 &= ~0x02):(PWMA_CR1 |= 0x02)) //½ûÖ¹¸üР0£º²úÉú¸üУ¨UEV£©Ê¼þ£»1£º²»²úÉú¸üÐÂʼþ +#define PWMA_CEN_Enable() PWMA_CR1 |= 0x01 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWMA_CEN_Disable() PWMA_CR1 &= ~0x01 //0£º½ûÖ¹¼ÆÊýÆ÷ + +#define PWMB_AlignMode_Edge() PWMB_CR1 = (PWMB_CR1 & ~0x60) +#define PWMB_AlignMode_Mid1() PWMB_CR1 = (PWMB_CR1 & ~0x60) | 0x20 +#define PWMB_AlignMode_Mid2() PWMB_CR1 = (PWMB_CR1 & ~0x60) | 0x40 +#define PWMB_AlignMode_Mid3() PWMB_CR1 = (PWMB_CR1 | 0x60) +#define PWMB_DIR_UP() PWMB_CR1 &= ~0x10 +#define PWMB_DIR_DN() PWMB_CR1 |= 0x10 +#define PWMB_OPMB(n) (n==0?(PWMB_CR1 &= ~0x08):(PWMB_CR1 |= 0x08)) //µ¥Âö³åģʽ 0£ºÔÚ·¢Éú¸üÐÂʼþʱ£¬¼ÆÊýÆ÷²»Í£Ö¹£»1£ºÔÚ·¢ÉúÏÂÒ»´Î¸üÐÂʼþʱ£¬Çå³ý CEN 룬¼ÆÊýÆ÷Í£Ö¹ +#define PWMB_URSB(n) (n==0?(PWMB_CR1 &= ~0x04):(PWMB_CR1 |= 0x04)) //¸üÐÂÇëÇóÔ´ +#define PWMB_UDISB(n) (n==0?(PWMB_CR1 &= ~0x02):(PWMB_CR1 |= 0x02)) //½ûÖ¹¸üР0£º²úÉú¸üУ¨UEV£©Ê¼þ£»1£º²»²úÉú¸üÐÂʼþ +#define PWMB_CEN_Enable() PWMB_CR1 |= 0x01 //1£ºÊ¹ÄܼÆÊýÆ÷ +#define PWMB_CEN_Disable() PWMB_CR1 &= ~0x01 //0£º½ûÖ¹¼ÆÊýÆ÷ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CR2 = 0xFEC1H; TI1S MMSA2 MMSA1 MMSA0 - COMSA - CCPCA 0000,x0x0 /* ¿ØÖƼĴæÆ÷ 2 */ +//sfr PWMB_CR2 = 0xFEE1H; TI5S MMSB2 MMSB1 MMSB0 - COMSB - CCPCB 0000,x0xx /* ¿ØÖƼĴæÆ÷ 2 */ +#define PWM1P_TI1() PWMA_CR2 &= ~0x80 +#define PWM1P2P3P_XOR_TI1() PWMA_CR2 |= 0x80 +#define PWM5P_TI2() PWMB_CR2 &= ~0x80 +#define PWM5P6P7P_XOR_TI2() PWMB_CR2 |= 0x80 + +#define MMSn_RESET 0 //¸´Î» +#define MMSn_ENABLE 1 //ʹÄÜ +#define MMSn_UPDATE 2 //¸üР+#define MMSn_COMP_TRGO 3 //±È½ÏÂö³å +#define MMSn_OC1REF_TRGO 4 //±È½Ï +#define MMSn_OC2REF_TRGO 5 //±È½Ï +#define MMSn_OC3REF_TRGO 6 //±È½Ï +#define MMSn_OC4REF_TRGO 7 //±È½Ï + +#define PWMA_MainModeSel(n) PWMA_CR2 = (PWMA_CR2 & ~0x70) | (n<<4) //Ö÷ģʽѡÔñ +#define PWMB_MainModeSel(n) PWMB_CR2 = (PWMB_CR2 & ~0x70) | (n<<4) //Ö÷ģʽѡÔñ + +//0£ºµ± CCPC=1 ʱ£¬Ö»ÓÐÔÚ COMG λÖà 1 µÄʱºòÕâЩ¿ØÖÆλ²Å±»¸üР+//1£ºµ± CCPC=1 ʱ£¬Ö»ÓÐÔÚ COMG λÖà 1 »ò TRGI ·¢ÉúÉÏÉýÑصÄʱºòÕâЩ¿ØÖÆλ²Å±»¸üР+#define PWMA_COMSUpdateCtrl(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x04):(PWMA_CR2 |= 0x04)) //²¶»ñ/±È½Ï¿ØÖÆλµÄ¸üпØÖÆÑ¡Ôñ +#define PWMB_COMSUpdateCtrl(n) PWMB_CR2 = (n==0?(PWMB_CR2 &= ~0x04):(PWMB_CR2 |= 0x04)) //²¶»ñ/±È½Ï¿ØÖÆλµÄ¸üпØÖÆÑ¡Ôñ +//0£º CCIE£¬ CCINE£¬ CCiP£¬ CCiNP ºÍ OCIM λ²»ÊÇԤװÔØµÄ +//1£º CCIE£¬ CCINE£¬ CCiP£¬ CCiNP ºÍ OCIM λÊÇԤװÔصģ»ÉèÖøÃλºó£¬ËüÃÇÖ»ÔÚÉèÖÃÁË COMGλºó±»¸üС£ +#define PWMA_CCPCAPreloaded(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x01):(PWMA_CR2 |= 0x01)) //²¶»ñ/±È½ÏԤװÔØ¿ØÖÆλ(¸Ãλֻ¶Ô¾ßÓл¥²¹Êä³öµÄͨµÀÆð×÷ÓÃ) +#define PWMB_CCPCBPreloaded(n) PWMA_CR2 = (n==0?(PWMA_CR2 &= ~0x01):(PWMA_CR2 |= 0x01)) //²¶»ñ/±È½ÏԤװÔØ¿ØÖÆλ(¸Ãλֻ¶Ô¾ßÓл¥²¹Êä³öµÄͨµÀÆð×÷ÓÃ) + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_SMCR = 0xFEC2H; MSMA TSA2 TSA1 TSA0 - SMSA2 SMSA1 SMSA0 0000,x000 /* ´Óģʽ¿ØÖƼĴæÆ÷ */ +//sfr PWMB_SMCR = 0xFEE2H; MSMB TSB2 TSB1 TSB0 - SMSB2 SMSB1 SMSB0 0000,x000 /* ´Óģʽ¿ØÖƼĴæÆ÷ */ +#define SMCR_TSn_ITR2 2 +#define SMCR_TSn_EDGE 4 +#define SMCR_TSn_TIMER1 5 +#define SMCR_TSn_TIMER2 6 +#define SMCR_TSn_ETRF 7 + +#define PWMA_SMCR_Source(n) PWMA_SMCR = (PWMA_SMCR & ~0x70) | (n<<4) //´¥·¢Ô´Ñ¡Ôñ +#define PWMB_SMCR_Source(n) PWMB_SMCR = (PWMB_SMCR & ~0x70) | (n<<4) //´¥·¢Ô´Ñ¡Ôñ + +#define SMCR_SMSA_INSIDE_CLK 0 +#define SMCR_SMSA_ENCODER_M1 1 +#define SMCR_SMSA_ENCODER_M2 2 +#define SMCR_SMSA_ENCODER_M3 3 +#define SMCR_SMSA_RESET 4 +#define SMCR_SMSA_GATE 5 +#define SMCR_SMSA_TRIG 6 +#define SMCR_SMSA_EXT_CLK 7 + +#define PWMA_SMCR_SMS(n) PWMA_SMCR = (PWMA_SMCR & ~0x07) | (n & 7) //ʱÖÓ/´¥·¢/´ÓģʽѡÔñ +#define PWMB_SMCR_SMS(n) PWMB_SMCR = (PWMB_SMCR & ~0x07) | (n & 7) //ʱÖÓ/´¥·¢/´ÓģʽѡÔñ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_ETR = 0xFEC3H; ETP1 ECE1 ETPS11 ETPS10 ETF13 ETF12 ETF11 ETF10 0000,0000 /* Íⲿ´¥·¢¼Ä´æÆ÷ */ +//sfr PWMB_ETR = 0xFEE3H; ETP2 ECE2 ETPS21 ETPS20 ETF23 ETF22 ETF21 ETF20 0000,0000 /* Íⲿ´¥·¢¼Ä´æÆ÷ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_IER = 0xFEC4H; BIEA TIEA COMIEA CC4IE CC3IE CC2IE CC1IE UIEA 0000,0000 /* ÖжÏʹÄܼĴæÆ÷ */ +//sfr PWMB_IER = 0xFEE4H; BIEB TIEB COMIEB CC8IE CC7IE CC6IE CC5IE UIEB 0000,0000 /* ÖжÏʹÄܼĴæÆ÷ */ +#define PWMA_UIEA_Enable() PWMA_IER |= 0x01 //1£ºÔÊÐí¸üÐÂÖÐ¶Ï +#define PWMA_UIEA_Disable() PWMA_IER &= ~0x01 //0£º½ûÖ¹¸üÐÂÖÐ¶Ï +#define PWMA_CC1IE_Enable() PWMA_IER |= 0x02 //1£ºÔÊÐí²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC1IE_Disable() PWMA_IER &= ~0x02 //0£º½ûÖ¹²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC2IE_Enable() PWMA_IER |= 0x04 //1£ºÔÊÐí²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC2IE_Disable() PWMA_IER &= ~0x04 //0£º½ûÖ¹²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC3IE_Enable() PWMA_IER |= 0x08 //1£ºÔÊÐí²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC3IE_Disable() PWMA_IER &= ~0x08 //0£º½ûÖ¹²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC4IE_Enable() PWMA_IER |= 0x10 //1£ºÔÊÐí²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_CC4IE_Disable() PWMA_IER &= ~0x10 //0£º½ûÖ¹²¶»ñ/±È½ÏÖÐ¶Ï +#define PWMA_COMIEA_Enable() PWMA_IER |= 0x20 //1£ºÔÊÐíCOMÖÐ¶Ï +#define PWMA_COMIEA_Disable() PWMA_IER &= ~0x20 //0£º½ûÖ¹COMÖÐ¶Ï +#define PWMA_TIEA_Enable() PWMA_IER |= 0x40 //1£ºÔÊÐí´¥·¢ÖÐ¶Ï +#define PWMA_TIEA_Disable() PWMA_IER &= ~0x40 //0£º½ûÖ¹´¥·¢ÖÐ¶Ï +#define PWMA_BIEA_Enable() PWMA_IER |= 0x80 //1£ºÔÊÐíɲ³µÖÐ¶Ï +#define PWMA_BIEA_Disable() PWMA_IER &= ~0x80 //0£º½ûֹɲ³µÖÐ¶Ï + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_SR1 = 0xFEC5H; BIF1 TIF1 COMIF1 CC4IF CC3IF CC2IF CC1IF UIF1 0000,0000 /* ״̬¼Ä´æÆ÷ 1 */ +//sfr PWMB_SR1 = 0xFEE5H; BIF2 TIF2 COMIF2 CC8IF CC7IF CC6IF CC5IF UIF2 0000,0000 /* ״̬¼Ä´æÆ÷ 1 */ +#define UIF1 1 +#define CC1IF (1<<1) +#define CC2IF (1<<2) +#define CC3IF (1<<3) +#define CC4IF (1<<4) +#define COMIF1 (1<<5) +#define TIF1 (1<<6) +#define BIF1 (1<<7) + +#define UIF2 1 +#define CC5IF (1<<1) +#define CC6IF (1<<2) +#define CC7IF (1<<3) +#define CC8IF (1<<4) +#define COMIF2 (1<<5) +#define TIF2 (1<<6) +#define BIF2 (1<<7) + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_SR2 = 0xFEC6H; - - - CC4OF CC3OF CC2OF CC1OF - xxx0,000x /* ״̬¼Ä´æÆ÷ 2 */ +//sfr PWMB_SR2 = 0xFEE6H; - - - CC8OF CC7OF CC6OF CC5OF - xxx0,000x /* ״̬¼Ä´æÆ÷ 2 */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_EGR = 0xFEC7H; BG1 TG1 COMG1 CC4G CC3G CC2G CC1G UG1 0000,0000 /* ʼþ²úÉú¼Ä´æÆ÷ */ +//sfr PWMB_EGR = 0xFEE7H; BG2 TG2 COMG2 CC8G CC7G CC6G CC5G UG2 0000,0000 /* ʼþ²úÉú¼Ä´æÆ÷ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR1 = 0xFEC8H; OC1CE OC1M2 OC1M1 OC1M0 OC1PE OC1FE CC1S1 CC1S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 1 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ +//sfr PWMB_CCMR1 = 0xFEE8H; OC5CE OC5M2 OC5M1 OC5M0 OC5PE OC5FE CC5S1 CC5S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 1 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ +#define OCnCE (1<<7) + +#define CCMRn_FREEZE 0x00 //¶³½á +#define CCMRn_MATCH_VALID 0x10 //Æ¥ÅäʱÉèÖÃͨµÀ n µÄÊä³öΪÓÐЧµçƽ +#define CCMRn_MATCH_INVALID 0x20 //Æ¥ÅäʱÉèÖÃͨµÀ n µÄÊä³öΪÎÞЧµçƽ +#define CCMRn_ROLLOVER 0x30 //·­×ª +#define CCMRn_FORCE_INVALID 0x40 //Ç¿ÖÆΪÎÞЧµçƽ +#define CCMRn_FORCE_VALID 0x50 //Ç¿ÖÆΪÓÐЧµçƽ +#define CCMRn_PWM_MODE1 0x60 //PWM ģʽ 1 +#define CCMRn_PWM_MODE2 0x70 //PWM ģʽ 2 + +#define PWMA_OC1ModeSet(n) PWMA_CCMR1 = (PWMA_CCMR1 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà +#define PWMB_OC5ModeSet(n) PWMB_CCMR1 = (PWMB_CCMR1 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà + +#define PWMA_OC1_ReloadEnable() PWMA_CCMR1 |= 0x08 //1£º¿ªÆô OC1PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMA_OC1_RelosdDisable() PWMA_CCMR1 &= ~0x08 //0£º½ûÖ¹ OC1PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC5_ReloadEnable() PWMB_CCMR1 |= 0x08 //1£º¿ªÆô OC5PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC5_RelosdDisable() PWMB_CCMR1 &= ~0x08 //0£º½ûÖ¹ OC5PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ + +#define PWMA_OC1_FastEnable() PWMA_CCMR1 |= 0x04 //1£º¿ªÆô OC1FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMA_OC1_FastDisable() PWMA_CCMR1 &= ~0x04 //0£º½ûÖ¹ OC1FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC5_FastEnable() PWMB_CCMR1 |= 0x04 //1£º¿ªÆô OC5FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC5_FastDisable() PWMB_CCMR1 &= ~0x04 //0£º½ûÖ¹ OC5FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ + +#define CCAS_OUTPUT 0x00 //Êä³ö +#define CCAS_IUTPUT_TI1FP1 0x01 //ÊäÈ룬IC1/IC2/IC3/IC4 Ó³ÉäÔÚ TI1FP1 ÉÏ +#define CCAS_IUTPUT_TI2FP1 0x02 //ÊäÈ룬IC1/IC2/IC3/IC4 Ó³ÉäÔÚ TI2FP1 ÉÏ +#define CCAS_IUTPUT_TRC 0x03 //ÊäÈ룬IC1/IC2/IC3/IC4 Ó³ÉäÔÚ TRC ÉÏ +#define CCBS_OUTPUT 0x00 //Êä³ö +#define CCBS_IUTPUT_TI5FP5 0x01 //ÊäÈ룬IC5/IC6/IC7/IC8 Ó³ÉäÔÚ TI5FP5 ÉÏ +#define CCBS_IUTPUT_TI6FP5 0x02 //ÊäÈ룬IC5/IC6/IC7/IC8 Ó³ÉäÔÚ TI6FP5 ÉÏ +#define CCBS_IUTPUT_TRC 0x03 //ÊäÈ룬IC5/IC6/IC7/IC8 Ó³ÉäÔÚ TRC ÉÏ + +#define PWMA_CC1S_Direction(n) PWMA_CCMR1 = (PWMA_CCMR1 & ~0x03) | (n) //²¶»ñ/±È½Ï 1 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ +#define PWMB_CC5S_Direction(n) PWMB_CCMR1 = (PWMB_CCMR1 & ~0x03) | (n) //²¶»ñ/±È½Ï 5 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR1 = 0xFEC8H; IC1F3 IC1F2 IC1F1 IC1F0 IC1PSC1 IC1PSC0 CC1S1 CC1S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 1 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ +//sfr PWMB_CCMR1 = 0xFEE8H; IC5F3 IC5F2 IC5F1 IC5F0 IC5PSC1 IC5PSC0 CC5S1 CC5S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 1 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ + +#define ICnF_01_Clock 0 +#define ICnF_02_Clock 1 +#define ICnF_04_Clock 2 +#define ICnF_08_Clock 3 +#define ICnF_12_Clock 4 +#define ICnF_16_Clock 5 +#define ICnF_24_Clock 6 +#define ICnF_32_Clock 7 +#define ICnF_48_Clock 8 +#define ICnF_64_Clock 9 +#define ICnF_80_Clock 10 +#define ICnF_96_Clock 11 +#define ICnF_128_Clock 12 +#define ICnF_160_Clock 13 +#define ICnF_192_Clock 14 +#define ICnF_256_Clock 15 + +#define PWMA_IC1F_FilterClock(n) PWMA_CCMR1 = (PWMA_CCMR1 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 1 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È +#define PWMB_IC5F_FilterClock(n) PWMB_CCMR1 = (PWMB_CCMR1 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 5 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È + +#define PWMA_IC1PSC_PrescalerSet(n) PWMA_CCMR1 = (PWMA_CCMR1 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 1 Ô¤·ÖƵÆ÷£¬0~3 +#define PWMB_IC5PSC_PrescalerSet(n) PWMB_CCMR1 = (PWMB_CCMR1 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 5 Ô¤·ÖƵÆ÷£¬0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR2 = 0xFEC9H; OC2CE OC2M2 OC2M1 OC2M0 OC2PE OC2FE CC2S1 CC2S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 2 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ +//sfr PWMB_CCMR2 = 0xFEE9H; OC6CE OC6M2 OC6M1 OC6M0 OC6PE OC6FE CC6S1 CC6S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 2 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ + +#define PWMA_OC2ModeSet(n) PWMA_CCMR2 = (PWMA_CCMR2 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà +#define PWMB_OC6ModeSet(n) PWMB_CCMR2 = (PWMB_CCMR2 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà + +#define PWMA_OC2_ReloadEnable() PWMA_CCMR2 |= 0x08 //1£º¿ªÆô OC2PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMA_OC2_RelosdDisable() PWMA_CCMR2 &= ~0x08 //0£º½ûÖ¹ OC2PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC6_ReloadEnable() PWMB_CCMR2 |= 0x08 //1£º¿ªÆô OC6PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC6_RelosdDisable() PWMB_CCMR2 &= ~0x08 //0£º½ûÖ¹ OC6PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ + +#define PWMA_OC2_FastEnable() PWMA_CCMR2 |= 0x04 //1£º¿ªÆô OC2FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMA_OC2_FastDisable() PWMA_CCMR2 &= ~0x04 //0£º½ûÖ¹ OC2FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC6_FastEnable() PWMB_CCMR2 |= 0x04 //1£º¿ªÆô OC6FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC6_FastDisable() PWMB_CCMR2 &= ~0x04 //0£º½ûÖ¹ OC6FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ + +#define PWMA_CC2S_Direction(n) PWMA_CCMR2 = (PWMA_CCMR2 & ~0x03) | (n) //²¶»ñ/±È½Ï 2 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ +#define PWMB_CC6S_Direction(n) PWMB_CCMR2 = (PWMB_CCMR2 & ~0x03) | (n) //²¶»ñ/±È½Ï 6 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR2 = 0xFEC9H; IC2F3 IC2F2 IC2F1 IC2F0 IC2PSC1 IC2PSC0 CC2S1 CC2S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 2 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ +//sfr PWMB_CCMR2 = 0xFEE9H; IC6F3 IC6F2 IC6F1 IC6F0 IC6PSC1 IC6PSC0 CC6S1 CC6S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 2 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ + +#define PWMA_IC2F_FilterClock(n) PWMA_CCMR2 = (PWMA_CCMR2 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 2 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È +#define PWMB_IC6F_FilterClock(n) PWMB_CCMR2 = (PWMB_CCMR2 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 6 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È + +#define PWMA_IC2PSC_PrescalerSet(n) PWMA_CCMR2 = (PWMA_CCMR2 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 2 Ô¤·ÖƵÆ÷£¬0~3 +#define PWMB_IC6PSC_PrescalerSet(n) PWMB_CCMR2 = (PWMB_CCMR2 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 6 Ô¤·ÖƵÆ÷£¬0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR3 = 0xFECAH; OC3CE OC3M2 OC3M1 OC3M0 OC3PE OC3FE CC3S1 CC3S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 3 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ +//sfr PWMB_CCMR3 = 0xFEEAH; OC7CE OC7M2 OC7M1 OC7M0 OC7PE OC7FE CC7S1 CC7S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 3 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ + +#define PWMA_OC3ModeSet(n) PWMA_CCMR3 = (PWMA_CCMR3 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà +#define PWMB_OC7ModeSet(n) PWMB_CCMR3 = (PWMB_CCMR3 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà + +#define PWMA_OC3_ReloadEnable() PWMA_CCMR3 |= 0x08 //1£º¿ªÆô OC3PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMA_OC3_RelosdDisable() PWMA_CCMR3 &= ~0x08 //0£º½ûÖ¹ OC3PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC7_ReloadEnable() PWMB_CCMR3 |= 0x08 //1£º¿ªÆô OC7PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC7_RelosdDisable() PWMB_CCMR3 &= ~0x08 //0£º½ûÖ¹ OC7PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ + +#define PWMA_OC3_FastEnable() PWMA_CCMR3 |= 0x04 //1£º¿ªÆô OC3FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMA_OC3_FastDisable() PWMA_CCMR3 &= ~0x04 //0£º½ûÖ¹ OC3FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC7_FastEnable() PWMB_CCMR3 |= 0x04 //1£º¿ªÆô OC7FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC7_FastDisable() PWMB_CCMR3 &= ~0x04 //0£º½ûÖ¹ OC7FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ + +#define PWMA_CC3S_Direction(n) PWMA_CCMR3 = (PWMA_CCMR3 & ~0x03) | (n) //²¶»ñ/±È½Ï 3 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ +#define PWMB_CC7S_Direction(n) PWMB_CCMR3 = (PWMB_CCMR3 & ~0x03) | (n) //²¶»ñ/±È½Ï 7 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR3 = 0xFECAH; IC3F3 IC3F2 IC3F1 IC3F0 IC3PSC1 IC3PSC0 CC3S1 CC3S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 3 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ +//sfr PWMB_CCMR3 = 0xFEEAH; IC7F3 IC7F2 IC7F1 IC7F0 IC7PSC1 IC7PSC0 CC7S1 CC7S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 3 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ + +#define PWMA_IC3F_FilterClock(n) PWMA_CCMR3 = (PWMA_CCMR3 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 3 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È +#define PWMB_IC7F_FilterClock(n) PWMB_CCMR3 = (PWMB_CCMR3 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 7 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È + +#define PWMA_IC3PSC_PrescalerSet(n) PWMA_CCMR3 = (PWMA_CCMR3 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 3 Ô¤·ÖƵÆ÷£¬0~3 +#define PWMB_IC7PSC_PrescalerSet(n) PWMB_CCMR3 = (PWMB_CCMR3 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 7 Ô¤·ÖƵÆ÷£¬0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR4 = 0xFECBH; OC4CE OC4M2 OC4M1 OC4M0 OC4PE OC4FE CC4S1 CC4S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 4 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ +//sfr PWMB_CCMR4 = 0xFEEBH; OC8CE OC8M2 OC8M1 OC8M0 OC8PE OC8FE CC8S1 CC8S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 4 - ͨµÀÅäÖÃΪ±È½ÏÊä³öģʽ */ + +#define PWMA_OC4ModeSet(n) PWMA_CCMR4 = (PWMA_CCMR4 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà +#define PWMB_OC8ModeSet(n) PWMB_CCMR4 = (PWMB_CCMR4 & ~0x70) | (n) //Êä³ö±È½ÏģʽÉèÖà + +#define PWMA_OC4_ReloadEnable() PWMA_CCMR4 |= 0x08 //1£º¿ªÆô OC4PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMA_OC4_RelosdDisable() PWMA_CCMR4 &= ~0x08 //0£º½ûÖ¹ OC4PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC8_ReloadEnable() PWMB_CCMR4 |= 0x08 //1£º¿ªÆô OC8PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ +#define PWMB_OC8_RelosdDisable() PWMB_CCMR4 &= ~0x08 //0£º½ûÖ¹ OC8PE Êä³ö±È½ÏµÄԤװÔع¦ÄÜ + +#define PWMA_OC4_FastEnable() PWMA_CCMR4 |= 0x04 //1£º¿ªÆô OC4FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMA_OC4_FastDisable() PWMA_CCMR4 &= ~0x04 //0£º½ûÖ¹ OC4FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC8_FastEnable() PWMB_CCMR4 |= 0x04 //1£º¿ªÆô OC8FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ +#define PWMB_OC8_FastDisable() PWMB_CCMR4 &= ~0x04 //0£º½ûÖ¹ OC8FE Êä³ö±È½Ï¿ìËÙ¹¦ÄÜ + +#define PWMA_CC4S_Direction(n) PWMA_CCMR4 = (PWMA_CCMR4 & ~0x03) | (n) //²¶»ñ/±È½Ï 4 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ +#define PWMB_CC8S_Direction(n) PWMB_CCMR4 = (PWMB_CCMR4 & ~0x03) | (n) //²¶»ñ/±È½Ï 8 Ñ¡Ôñ¡£ÕâÁ½Î»¶¨ÒåͨµÀµÄ·½Ïò£¨ÊäÈë/Êä³ö£©£¬¼°ÊäÈë½ÅµÄÑ¡Ôñ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCMR4 = 0xFECBH; IC4F3 IC4F2 IC4F1 IC4F0 IC4PSC1 IC4PSC0 CC4S1 CC4S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 4 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ +//sfr PWMB_CCMR4 = 0xFEEBH; IC8F3 IC8F2 IC8F1 IC8F0 IC8PSC1 IC8PSC0 CC8S1 CC8S0 0000,0000 /* ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷ 4 - ͨµÀÅäÖÃΪ²¶»ñÊäÈëģʽ */ + +#define PWMA_IC4F_FilterClock(n) PWMA_CCMR4 = (PWMA_CCMR4 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 4 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È +#define PWMB_IC8F_FilterClock(n) PWMB_CCMR4 = (PWMB_CCMR4 & 0x0F) | (n<<4) //ÊäÈ벶»ñ 8 Â˲¨Æ÷Ñ¡Ôñ£¬¸ÃλÓò¶¨ÒåÁË TIn µÄ²ÉÑùƵÂʼ°Êý×ÖÂ˲¨Æ÷³¤¶È + +#define PWMA_IC4PSC_PrescalerSet(n) PWMA_CCMR4 = (PWMA_CCMR4 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 4 Ô¤·ÖƵÆ÷£¬0~3 +#define PWMB_IC8PSC_PrescalerSet(n) PWMB_CCMR4 = (PWMB_CCMR4 & 0xF3) | ((n&3)<<2) //ÊäÈë/²¶»ñ 8 Ô¤·ÖƵÆ÷£¬0~3 + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCER1 = 0xFECCH; CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E 0000,0000 /* ²¶»ñ/±È½ÏʹÄܼĴæÆ÷ 1 */ +//sfr PWMB_CCER1 = 0xFEECH; - - CC6P CC6E - - CC5P CC5E 0000,0000 /* ²¶»ñ/±È½ÏʹÄܼĴæÆ÷ 1 */ + +#define PWMA_CCER1_Disable() PWMA_CCER1 = 0x00 //¹Ø±ÕËùÓÐÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC1E_Enable() PWMA_CCER1 |= 0x01 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC1E_Disable() PWMA_CCER1 &= ~0x01 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC1P_LowValid() PWMA_CCER1 |= 0x02 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC1P_HighValid() PWMA_CCER1 &= ~0x02 //0£º¸ßµçƽÓÐЧ +#define PWMA_CC1P_CaptureRise() PWMA_CCER1 |= 0x02 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMA_CC1P_CaptureFall() PWMA_CCER1 &= ~0x02 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ +#define PWMA_CC1NE_Enable() PWMA_CCER1 |= 0x04 //1£º¿ªÆô±È½ÏÊä³ö +#define PWMA_CC1NE_Disable() PWMA_CCER1 &= ~0x04 //0£º¹Ø±Õ±È½ÏÊä³ö +#define PWMA_CC1NP_LowValid() PWMA_CCER1 |= 0x08 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC1NP_HighValid() PWMA_CCER1 &= ~0x08 //0£º¸ßµçƽÓÐЧ + +#define PWMA_CC2E_Enable() PWMA_CCER1 |= 0x10 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC2E_Disable() PWMA_CCER1 &= ~0x10 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC2P_LowValid() PWMA_CCER1 |= 0x20 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC2P_HighValid() PWMA_CCER1 &= ~0x20 //0£º¸ßµçƽÓÐЧ +#define PWMA_CC2P_CaptureRise() PWMA_CCER1 |= 0x20 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMA_CC2P_CaptureFall() PWMA_CCER1 &= ~0x20 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ +#define PWMA_CC2NE_Enable() PWMA_CCER1 |= 0x40 //1£º¿ªÆô±È½ÏÊä³ö +#define PWMA_CC2NE_Disable() PWMA_CCER1 &= ~0x40 //0£º¹Ø±Õ±È½ÏÊä³ö +#define PWMA_CC2NP_LowValid() PWMA_CCER1 |= 0x80 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC2NP_HighValid() PWMA_CCER1 &= ~0x80 //0£º¸ßµçƽÓÐЧ + +#define PWMB_CCER1_Disable() PWMB_CCER1 = 0x00 //¹Ø±ÕËùÓÐÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC5E_Enable() PWMB_CCER1 |= 0x01 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC5E_Disable() PWMB_CCER1 &= ~0x01 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC5P_LowValid() PWMB_CCER1 |= 0x02 //1£ºµÍµçƽÓÐЧ +#define PWMB_CC5P_HighValid() PWMB_CCER1 &= ~0x02 //0£º¸ßµçƽÓÐЧ +#define PWMB_CC5P_CaptureRise() PWMB_CCER1 |= 0x02 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMB_CC5P_CaptureFall() PWMB_CCER1 &= ~0x02 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ + +#define PWMB_CC6E_Enable() PWMB_CCER1 |= 0x10 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC6E_Disable() PWMB_CCER1 &= ~0x10 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC6P_LowValid() PWMB_CCER1 |= 0x20 //1£ºµÍµçƽÓÐЧ +#define PWMB_CC6P_HighValid() PWMB_CCER1 &= ~0x20 //0£º¸ßµçƽÓÐЧ +#define PWMB_CC6P_CaptureRise() PWMB_CCER1 |= 0x20 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMB_CC6P_CaptureFall() PWMB_CCER1 &= ~0x20 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCER2 = 0xFECDH; CC4NP CC4NE CC4P CC4E CC3NP CC3NE CC3P CC3E 0000,0000 /* ²¶»ñ/±È½ÏʹÄܼĴæÆ÷ 2 */ +//sfr PWMB_CCER2 = 0xFEEDH; - - CC8P CC8E - - CC7P CC7E 0000,0000 /* ²¶»ñ/±È½ÏʹÄܼĴæÆ÷ 2 */ + +#define PWMA_CCER2_Disable() PWMA_CCER2 = 0x00 //¹Ø±ÕËùÓÐÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC3E_Enable() PWMA_CCER2 |= 0x01 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC3E_Disable() PWMA_CCER2 &= ~0x01 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC3P_LowValid() PWMA_CCER2 |= 0x02 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC3P_HighValid() PWMA_CCER2 &= ~0x02 //0£º¸ßµçƽÓÐЧ +#define PWMA_CC3P_CaptureRise() PWMA_CCER2 |= 0x02 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMA_CC3P_CaptureFall() PWMA_CCER2 &= ~0x02 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ +#define PWMA_CC3NE_Enable() PWMA_CCER2 |= 0x04 //1£º¿ªÆô±È½ÏÊä³ö +#define PWMA_CC3NE_Disable() PWMA_CCER2 &= ~0x04 //0£º¹Ø±Õ±È½ÏÊä³ö +#define PWMA_CC3NP_LowValid() PWMA_CCER2 |= 0x08 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC3NP_HighValid() PWMA_CCER2 &= ~0x08 //0£º¸ßµçƽÓÐЧ + +#define PWMA_CC4E_Enable() PWMA_CCER2 |= 0x10 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC4E_Disable() PWMA_CCER2 &= ~0x10 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMA_CC4P_LowValid() PWMA_CCER2 |= 0x20 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC4P_HighValid() PWMA_CCER2 &= ~0x20 //0£º¸ßµçƽÓÐЧ +#define PWMA_CC4P_CaptureRise() PWMA_CCER2 |= 0x20 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMA_CC4P_CaptureFall() PWMA_CCER2 &= ~0x20 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ +#define PWMA_CC4NE_Enable() PWMA_CCER2 |= 0x40 //1£º¿ªÆô±È½ÏÊä³ö +#define PWMA_CC4NE_Disable() PWMA_CCER2 &= ~0x40 //0£º¹Ø±Õ±È½ÏÊä³ö +#define PWMA_CC4NP_LowValid() PWMA_CCER2 |= 0x80 //1£ºµÍµçƽÓÐЧ +#define PWMA_CC4NP_HighValid() PWMA_CCER2 &= ~0x80 //0£º¸ßµçƽÓÐЧ + +#define PWMB_CCER2_Disable() PWMB_CCER2 = 0x00 //¹Ø±ÕËùÓÐÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC7E_Enable() PWMB_CCER2 |= 0x01 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC7E_Disable() PWMB_CCER2 &= ~0x01 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC7P_LowValid() PWMB_CCER2 |= 0x02 //1£ºµÍµçƽÓÐЧ +#define PWMB_CC7P_HighValid() PWMB_CCER2 &= ~0x02 //0£º¸ßµçƽÓÐЧ +#define PWMB_CC7P_CaptureRise() PWMB_CCER2 |= 0x02 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMB_CC7P_CaptureFall() PWMB_CCER2 &= ~0x02 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ + +#define PWMB_CC8E_Enable() PWMB_CCER2 |= 0x10 //1£º¿ªÆôÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC8E_Disable() PWMB_CCER2 &= ~0x10 //0£º¹Ø±ÕÊäÈ벶»ñ/±È½ÏÊä³ö +#define PWMB_CC8P_LowValid() PWMB_CCER2 |= 0x20 //1£ºµÍµçƽÓÐЧ +#define PWMB_CC8P_HighValid() PWMB_CCER2 &= ~0x20 //0£º¸ßµçƽÓÐЧ +#define PWMB_CC8P_CaptureRise() PWMB_CCER2 |= 0x20 //1£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄϽµÑØ +#define PWMB_CC8P_CaptureFall() PWMB_CCER2 &= ~0x20 //0£º²¶»ñ·¢ÉúÔÚ TI1F »ò TI2F µÄÉÏÉýÑØ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CNTRH = 0xFECEH; CNT1[15:8] 0000,0000 /* ¼ÆÊýÆ÷¸ß 8 λ */ +//sfr PWMB_CNTRH = 0xFEEEH; CNT2[15:8] 0000,0000 /* ¼ÆÊýÆ÷¸ß 8 λ */ +//sfr PWMA_CNTRL = 0xFECFH; CNT1[7:0] 0000,0000 /* ¼ÆÊýÆ÷µÍ 8 λ */ +//sfr PWMB_CNTRL = 0xFEEFH; CNT2[7:0] 0000,0000 /* ¼ÆÊýÆ÷µÍ 8 λ */ + +#define PWMA_Counter(n) PWMA_CNTR = n //¼ÆÊýÆ÷ÉèÖà +#define PWMB_Counter(n) PWMB_CNTR = n //¼ÆÊýÆ÷ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_PSCRH = 0xFED0H; PSC1[15:8] 0000,0000 /* Ô¤·ÖƵÆ÷¸ß 8 λ */ +//sfr PWMB_PSCRH = 0xFEF0H; PSC2[15:8] 0000,0000 /* Ô¤·ÖƵÆ÷¸ß 8 λ */ +//sfr PWMA_PSCRL = 0xFED1H; PSC1[7:0] 0000,0000 /* Ô¤·ÖƵÆ÷µÍ 8 λ */ +//sfr PWMB_PSCRL = 0xFEF1H; PSC2[7:0] 0000,0000 /* Ô¤·ÖƵÆ÷µÍ 8 λ */ + +#define PWMA_Prescaler(n) PWMA_PSCR = n //Ô¤·ÖƵÆ÷ÉèÖà +#define PWMB_Prescaler(n) PWMB_PSCR = n //Ô¤·ÖƵÆ÷ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_ARRH = 0xFED2H; ARR1[15:8] 0000,0000 /* ×Ô¶¯ÖØ×°ÔؼĴæÆ÷¸ß 8 λ */ +//sfr PWMB_ARRH = 0xFEF2H; ARR2[15:8] 0000,0000 /* ×Ô¶¯ÖØ×°ÔؼĴæÆ÷¸ß 8 λ */ +//sfr PWMA_ARRL = 0xFED3H; ARR1[7:0] 0000,0000 /* ×Ô¶¯ÖØ×°ÔؼĴæÆ÷µÍ 8 λ */ +//sfr PWMB_ARRL = 0xFEF3H; ARR2[7:0] 0000,0000 /* ×Ô¶¯ÖØ×°ÔؼĴæÆ÷µÍ 8 λ */ + +#define PWMA_AutoReload(n) PWMA_ARR = n //×Ô¶¯ÖØ×°ÔؼĴæÆ÷ÉèÖà +#define PWMB_AutoReload(n) PWMB_ARR = n //×Ô¶¯ÖØ×°ÔؼĴæÆ÷ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_RCR = 0xFED4H; REP1[7:0] 0000,0000 /* Öظ´¼ÆÊýÆ÷¼Ä´æÆ÷ */ +//sfr PWMB_RCR = 0xFEF4H; REP2[7:0] 0000,0000 /* Öظ´¼ÆÊýÆ÷¼Ä´æÆ÷ */ + +#define PWMA_ReCounter(n) PWMA_RCR = n //Öظ´¼ÆÊýÆ÷¼Ä´æÆ÷ÉèÖà +#define PWMB_ReCounter(n) PWMB_RCR = n //Öظ´¼ÆÊýÆ÷¼Ä´æÆ÷ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR1H = 0xFED5H; CCR1[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 1 ¸ß 8 λ */ +//sfr PWMB_CCR5H = 0xFEF5H; CCR5[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 1 ¸ß 8 λ */ +//sfr PWMA_CCR1L = 0xFED6H; CCR1[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 1 µÍ 8 λ */ +//sfr PWMB_CCR5L = 0xFEF6H; CCR5[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 1 µÍ 8 λ */ + +#define PWMA_Duty1(n) PWMA_CCR1 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 1 ÉèÖà +#define PWMB_Duty5(n) PWMB_CCR5 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 1 ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR2H = 0xFED7H; CCR2[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 2 ¸ß 8 λ */ +//sfr PWMB_CCR6H = 0xFEF7H; CCR6[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 2 ¸ß 8 λ */ +//sfr PWMA_CCR2L = 0xFED8H; CCR2[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 2 µÍ 8 λ */ +//sfr PWMB_CCR6L = 0xFEF8H; CCR6[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 2 µÍ 8 λ */ + +#define PWMA_Duty2(n) PWMA_CCR2 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 2 ÉèÖà +#define PWMB_Duty6(n) PWMB_CCR6 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 2 ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR3H = 0xFED9H; CCR3[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 3 ¸ß 8 λ */ +//sfr PWMB_CCR7H = 0xFEF9H; CCR7[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 3 ¸ß 8 λ */ +//sfr PWMA_CCR3L = 0xFEDAH; CCR3[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 3 µÍ 8 λ */ +//sfr PWMB_CCR7L = 0xFEFAH; CCR7[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 3 µÍ 8 λ */ + +#define PWMA_Duty3(n) PWMA_CCR3 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 3 ÉèÖà +#define PWMB_Duty7(n) PWMB_CCR7 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 3 ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_CCR4H = 0xFEDBH; CCR4[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 4 ¸ß 8 λ */ +//sfr PWMB_CCR8H = 0xFEFBH; CCR8[15:8] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 4 ¸ß 8 λ */ +//sfr PWMA_CCR4L = 0xFEDCH; CCR4[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 4 µÍ 8 λ */ +//sfr PWMB_CCR8L = 0xFEFCH; CCR8[7:0] 0000,0000 /* ²¶»ñ/±È½Ï¼Ä´æÆ÷ 4 µÍ 8 λ */ + +#define PWMA_Duty4(n) PWMA_CCR4 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 4 ÉèÖà +#define PWMB_Duty8(n) PWMB_CCR8 = n //²¶»ñ/±È½Ï¼Ä´æÆ÷ 4 ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_BRK = 0xFEDDH; MOE1 AOE1 BKP1 BKE1 OSSR1 OSSI1 LOCK11 LOCK10 0000,0000 /* ɲ³µ¼Ä´æÆ÷ */ +//sfr PWMB_BRK = 0xFEFDH; MOE2 AOE2 BKP2 BKE2 OSSR2 OSSI2 LOCK21 LOCK20 0000,0000 /* ɲ³µ¼Ä´æÆ÷ */ + +#define PWMA_BrakeOutputEnable() PWMA_BRK |= 0x80 //1£ºÖ÷Êä³öʹÄÜ +#define PWMA_BrakeOutputDisable() PWMA_BRK &= ~0x80 //0£ºÖ÷Êä³ö½ûÖ¹ +#define PWMB_BrakeOutputEnable() PWMB_BRK |= 0x80 //1£ºÖ÷Êä³öʹÄÜ +#define PWMB_BrakeOutputDisable() PWMB_BRK &= ~0x80 //0£ºÖ÷Êä³ö½ûÖ¹ + +#define PWMA_BrakeAutoOutputEnable() PWMA_BRK |= 0x40 //1£º×Ô¶¯Êä³öʹÄÜ +#define PWMA_BrakeAutoOutputDisable() PWMA_BRK &= ~0x40 //0£º×Ô¶¯Êä³ö½ûÖ¹ +#define PWMB_BrakeAutoOutputEnable() PWMB_BRK |= 0x40 //1£º×Ô¶¯Êä³öʹÄÜ +#define PWMB_BrakeAutoOutputDisable() PWMB_BRK &= ~0x40 //0£º×Ô¶¯Êä³ö½ûÖ¹ + +#define PWMA_BrakeHighValid() PWMA_BRK |= 0x20 //1£ºÉ²³µÊäÈë¸ßµçƽÓÐЧ +#define PWMA_BrakeLowValid() PWMA_BRK &= ~0x20 //0£ºÉ²³µÊäÈëµÍµçƽÓÐЧ +#define PWMB_BrakeHighValid() PWMB_BRK |= 0x20 //1£ºÉ²³µÊäÈë¸ßµçƽÓÐЧ +#define PWMB_BrakeLowValid() PWMB_BRK &= ~0x20 //0£ºÉ²³µÊäÈëµÍµçƽÓÐЧ + +#define PWMA_BrakeEnable() PWMA_BRK |= 0x10 //1£º¿ªÆôɲ³µÊäÈë +#define PWMA_BrakeDisable() PWMA_BRK &= ~0x10 //0£º½ûֹɲ³µÊäÈë +#define PWMB_BrakeEnable() PWMB_BRK |= 0x10 //1£º¿ªÆôɲ³µÊäÈë +#define PWMB_BrakeDisable() PWMB_BRK &= ~0x10 //0£º½ûֹɲ³µÊäÈë + +//ÔËÐÐģʽÏ¡°¹Ø±Õ״̬¡±Ñ¡Ôñ +#define PWMA_OSSRnEnable() PWMA_BRK |= 0x08 //1£ºµ± PWM ²»¹¤×÷ʱ£¬Ò»µ© CCiE=1 »ò CCiNE=1£¬Ê×ÏÈ¿ªÆô OC/OCN ²¢Êä³öÎÞЧµçƽ£¬È»ºóÖÃOC/OCN ʹÄÜÊä³öÐźÅ=1 +#define PWMA_OSSRnDisable() PWMA_BRK &= ~0x08 //0£ºµ± PWM ²»¹¤×÷ʱ£¬½ûÖ¹ OC/OCN Êä³ö£¨OC/OCN ʹÄÜÊä³öÐźÅ=0£© +#define PWMB_OSSRnEnable() PWMB_BRK |= 0x08 //1£ºµ± PWM ²»¹¤×÷ʱ£¬Ò»µ© CCiE=1 »ò CCiNE=1£¬Ê×ÏÈ¿ªÆô OC/OCN ²¢Êä³öÎÞЧµçƽ£¬È»ºóÖÃOC/OCN ʹÄÜÊä³öÐźÅ=1 +#define PWMB_OSSRnDisable() PWMB_BRK &= ~0x08 //0£ºµ± PWM ²»¹¤×÷ʱ£¬½ûÖ¹ OC/OCN Êä³ö£¨OC/OCN ʹÄÜÊä³öÐźÅ=0£© +//¿ÕÏÐģʽÏ¡°¹Ø±Õ״̬¡±Ñ¡Ôñ +#define PWMA_OSSInEnable() PWMA_BRK |= 0x04 //1£ºµ± PWM ²»¹¤×÷ʱ£¬Ò»µ© CCiE=1 »ò CCiNE=1£¬OC/OCN Ê×ÏÈÊä³öÆä¿ÕÏеçƽ£¬È»ºó OC/OCNʹÄÜÊä³öÐźÅ=1 +#define PWMA_OSSInDisable() PWMA_BRK &= ~0x04 //0£ºµ± PWM ²»¹¤×÷ʱ£¬½ûÖ¹ OC/OCN Êä³ö£¨OC/OCN ʹÄÜÊä³öÐźÅ=0£© +#define PWMB_OSSInEnable() PWMB_BRK |= 0x04 //1£ºµ± PWM ²»¹¤×÷ʱ£¬Ò»µ© CCiE=1 »ò CCiNE=1£¬OC/OCN Ê×ÏÈÊä³öÆä¿ÕÏеçƽ£¬È»ºó OC/OCNʹÄÜÊä³öÐźÅ=1 +#define PWMB_OSSInDisable() PWMB_BRK &= ~0x04 //0£ºµ± PWM ²»¹¤×÷ʱ£¬½ûÖ¹ OC/OCN Êä³ö£¨OC/OCN ʹÄÜÊä³öÐźÅ=0£© + +#define PWMn_lock_L0 0 //¼Ä´æÆ÷ÎÞд±£»¤ +#define PWMn_lock_L1 1 //Ëø¶¨¼¶±ð 1£º²»ÄÜдÈë PWMn_BKR ¼Ä´æÆ÷µÄ BKE¡¢BKP¡¢AOE λºÍPWMn_OISR ¼Ä´æÆ÷µÄ OISI λ +#define PWMn_lock_L2 2 //Ëø¶¨¼¶±ð 2£º²»ÄÜдÈëËø¶¨¼¶±ð 1 Öеĸ÷룬Ҳ²»ÄÜдÈë CC ¼«ÐÔλÒÔ¼° OSSR/OSSI λ +#define PWMn_lock_L3 3 //Ëø¶¨¼¶±ð 3£º²»ÄÜдÈëËø¶¨¼¶±ð 2 Öеĸ÷룬Ҳ²»ÄÜдÈë CC ¿ØÖÆλ + +#define PWMA_LockLevelSet(n) PWMA_BRK = (PWMA_BRK & ~0x03) | (n&3) //Ëø¶¨ÉèÖ᣸ÃλΪ·ÀÖ¹Èí¼þ´íÎó¶øÌṩµÄд±£»¤´ëÊ© +#define PWMB_LockLevelSet(n) PWMB_BRK = (PWMB_BRK & ~0x03) | (n&3) //Ëø¶¨ÉèÖ᣸ÃλΪ·ÀÖ¹Èí¼þ´íÎó¶øÌṩµÄд±£»¤´ëÊ© + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_DTR = 0xFEDEH; DTG1[7:0] 0000,0000 /* ËÀÇø¼Ä´æÆ÷ */ +//sfr PWMB_DTR = 0xFEFEH; DTG2[7:0] 0000,0000 /* ËÀÇø¼Ä´æÆ÷ */ + +//DTGn[7:5] = 000~011: ËÀÇøʱ¼ä = DTGn[7:0] * tCK_PSC +//DTGn[7:5] = 100~101: ËÀÇøʱ¼ä = (64 + DTGn[6:0]) * 2 * tCK_PSC +//DTGn[7:5] = 110: ËÀÇøʱ¼ä = (32 + DTGn[5:0]) * 8 * tCK_PSC +//DTGn[7:5] = 111: ËÀÇøʱ¼ä = (32 + DTGn[4:0]) * 16 * tCK_PSC + +#define PWMA_DeadTime(n) PWMA_DTR = n //ËÀÇø·¢ÉúÆ÷ÉèÖà +#define PWMB_DeadTime(n) PWMB_DTR = n //ËÀÇø·¢ÉúÆ÷ÉèÖà + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr PWMA_OISR = 0xFEDFH; OIS4N OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 0000,0000 /* Êä³ö¿ÕÏÐ״̬¼Ä´æÆ÷ */ +//sfr PWMB_OISR = 0xFEFFH; - OIS8 - OIS7 - OIS6 - OIS5 x0x0,x0x0 /* Êä³ö¿ÕÏÐ״̬¼Ä´æÆ÷ */ + +#define PWMA_OC1_OUT_0() PWMA_OISR &= ~0x01 /* µ± MOE=0 ʱ£¬Èç¹û OC1N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC1=0 */ +#define PWMA_OC1_OUT_1() PWMA_OISR |= 0x01 /* µ± MOE=0 ʱ£¬Èç¹û OC1N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC1=1 */ +#define PWMA_OC1N_OUT_0() PWMA_OISR &= ~0x02 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC1N=0 */ +#define PWMA_OC1N_OUT_1() PWMA_OISR |= 0x02 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC1N=1 */ +#define PWMA_OC2_OUT_0() PWMA_OISR &= ~0x04 /* µ± MOE=0 ʱ£¬Èç¹û OC2N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC2=0 */ +#define PWMA_OC2_OUT_1() PWMA_OISR |= 0x04 /* µ± MOE=0 ʱ£¬Èç¹û OC2N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC2=1 */ +#define PWMA_OC2N_OUT_0() PWMA_OISR &= ~0x08 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC2N=0 */ +#define PWMA_OC2N_OUT_1() PWMA_OISR |= 0x08 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC2N=1 */ +#define PWMA_OC3_OUT_0() PWMA_OISR &= ~0x10 /* µ± MOE=0 ʱ£¬Èç¹û OC3N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC3=0 */ +#define PWMA_OC3_OUT_1() PWMA_OISR |= 0x10 /* µ± MOE=0 ʱ£¬Èç¹û OC3N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC3=1 */ +#define PWMA_OC3N_OUT_0() PWMA_OISR &= ~0x20 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC3N=0 */ +#define PWMA_OC3N_OUT_1() PWMA_OISR |= 0x20 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC3N=1 */ +#define PWMA_OC4_OUT_0() PWMA_OISR &= ~0x40 /* µ± MOE=0 ʱ£¬Èç¹û OC4N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC4=0 */ +#define PWMA_OC4_OUT_1() PWMA_OISR |= 0x40 /* µ± MOE=0 ʱ£¬Èç¹û OC4N ʹÄÜ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC4=1 */ +#define PWMA_OC4N_OUT_0() PWMA_OISR &= ~0x80 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC4N=0 */ +#define PWMA_OC4N_OUT_1() PWMA_OISR |= 0x80 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC4N=1 */ + +#define PWMB_OC5_OUT_0() PWMB_OISR &= ~0x01 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC5=0 */ +#define PWMB_OC5_OUT_1() PWMB_OISR |= 0x01 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC5=1 */ +#define PWMB_OC6_OUT_0() PWMB_OISR &= ~0x04 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC6=0 */ +#define PWMB_OC6_OUT_1() PWMB_OISR |= 0x04 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC6=1 */ +#define PWMB_OC7_OUT_0() PWMB_OISR &= ~0x10 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC7=0 */ +#define PWMB_OC7_OUT_1() PWMB_OISR |= 0x10 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC7=1 */ +#define PWMB_OC8_OUT_0() PWMB_OISR &= ~0x40 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC8=0 */ +#define PWMB_OC8_OUT_1() PWMB_OISR |= 0x40 /* µ± MOE=0 ʱ£¬ÔòÔÚÒ»¸öËÀÇøºó£¬OC8=1 */ + + + + +/* +;PCA_PWMn: 7 6 5 4 3 2 1 0 +; EBSn_1 EBSn_0 - - - - EPCnH EPCnL +;B5-B2: ±£Áô +;B1(EPCnH): ÔÚPWMģʽÏ£¬ÓëCCAPnH×é³É9λÊý¡£ +;B0(EPCnL): ÔÚPWMģʽÏ£¬ÓëCCAPnL×é³É9λÊý¡£ +*/ +#define PWM0_NORMAL() PCA_PWM0 &= ~3 /* PWM0Õý³£Êä³ö(ĬÈÏ) */ +#define PWM0_OUT_0() PCA_PWM0 |= 3, CCAP0H = 0xff /* PWM0Ò»Ö±Êä³ö0 */ +#define PWM0_OUT_1() PCA_PWM0 &= 0xc0, CCAP0H = 0 /* PWM0Ò»Ö±Êä³ö1 */ + +#define PWM1_NORMAL() PCA_PWM1 &= ~3 /* PWM1Õý³£Êä³ö(ĬÈÏ) */ +#define PWM1_OUT_0() PCA_PWM1 |= 3, CCAP1H = 0xff /* PWM1Ò»Ö±Êä³ö0 */ +#define PWM1_OUT_1() PCA_PWM1 &= 0xc0, CCAP1H = 0 /* PWM1Ò»Ö±Êä³ö1 */ + +#define PWM2_NORMAL() PCA_PWM2 &= ~3 /* PWM2Õý³£Êä³ö(ĬÈÏ) */ +#define PWM2_OUT_0() PCA_PWM2 |= 3, CCAP2H = 0xff /* PWM2Ò»Ö±Êä³ö0 */ +#define PWM2_OUT_1() PCA_PWM2 &= 0xc0, CCAP2H = 0 /* PWM2Ò»Ö±Êä³ö1 */ + +//#define PWM3_NORMAL() PCA_PWM3 &= ~3 /* PWM3Õý³£Êä³ö(ĬÈÏ) */ +//#define PWM3_OUT_0() PCA_PWM3 |= 3, CCAP3H = 0xff /* PWM3Ò»Ö±Êä³ö0 */ +//#define PWM3_OUT_1() PCA_PWM3 &= 0xc0, CCAP3H = 0 /* PWM3Ò»Ö±Êä³ö1 */ + + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CCON = 0xD8; CF CR - - CCF3 CCF2 CCF1 CCF0 00xx,xx00 //PCA ¿ØÖƼĴæÆ÷¡£ +sbit CCF0 = CCON^0; /* PCA Ä£¿é0ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£ */ +sbit CCF1 = CCON^1; /* PCA Ä£¿é1ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£ */ +sbit CCF2 = CCON^2; /* PCA Ä£¿é2ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£ */ +//sbit CCF3 = CCON^3; /* PCA Ä£¿é3ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£ */ +sbit CR = CCON^6; /* 1: ÔÊÐíPCA¼ÆÊýÆ÷¼ÆÊý£¬±ØÐëÓÉÈí¼þÇå0¡£*/ +sbit CF = CCON^7; /* PCA¼ÆÊýÆ÷Òç³ö£¨CH£¬CLÓÉFFFFH±äΪ0000H£©±êÖ¾¡£PCA¼ÆÊýÆ÷Òç³öºóÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£*/ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr CMOD = 0xD9; CIDL - - - CPS2 CPS1 CPS0 ECF 0xxx,0000 //PCA ¹¤×÷ģʽ¼Ä´æÆ÷¡£ +#define PCA_IDLE_OFF() CMOD |= (1<<7) /* IDLE״̬PCAÍ£Ö¹¼ÆÊý¡£ */ +#define PCA_IDLE_ON() CMOD &= ~(1<<7) /* IDLE״̬PCA¼ÌÐø¼ÆÊý¡£ */ +#define PCA_CLK_12T() CMOD &= ~0x0E /* PCA¼ÆÊýÂö³åÑ¡Ôñ fosc/12 */ +#define PCA_CLK_2T() CMOD = (CMOD & ~0x0E) + 2 /* PCA¼ÆÊýÂö³åÑ¡Ôñ fosc/2 */ +#define PCA_CLK_T0() CMOD = (CMOD & ~0x0E) + 4 /* PCA¼ÆÊýÂö³åÑ¡ÔñTimer0Öжϣ¬Timer0¿Éͨ¹ýAUXR¼Ä´æÆ÷ÉèÖóɹ¤×÷ÔÚ12T»ò1Tģʽ¡£ */ +#define PCA_CLK_ECI() CMOD = (CMOD & ~0x0E) + 6 /* PCA¼ÆÊýÂö³åÑ¡Ôñ´ÓECI/P3.4½ÅÊäÈëµÄÍⲿʱÖÓ£¬×î´ó fosc/2¡£ */ +#define PCA_CLK_1T() CMOD = (CMOD & ~0x0E) + 8 /* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc */ +#define PCA_CLK_4T() CMOD = (CMOD & ~0x0E) + 10 /* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc/4 */ +#define PCA_CLK_6T() CMOD = (CMOD & ~0x0E) + 12 /* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc/6 */ +#define PCA_CLK_8T() CMOD = (CMOD & ~0x0E) + 14 /* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc/8 */ +#define PCA_INT_ENABLE() CMOD |= 1 /* PCA¼ÆÊýÆ÷Òç³öÖжÏÔÊÐí룬1---ÔÊÐíCF£¨CCON.7£©²úÉúÖжϡ£ */ +#define PCA_INT_DISABLE() CMOD &= ~1 /* PCA¼ÆÊýÆ÷Òç³öÖжϽûÖ¹¡£ */ + +// 7 6 5 4 3 2 1 0 Reset Value +//sfr P_SW1 = 0xA2; S1_S1 S1_S0 CCP_S1 CCP_S0 SPI_S1 SPI_S0 0 - nn00,000x //Auxiliary Register 1 +#define PCA_USE_P12P11P10P37() P_SW1 &= ~0x30 /* ½«PCA/PWMÇл»µ½P12(ECI) P11(CCP0) P10(CCP1) P37(CCP2)(ÉϵçĬÈÏ) */ +#define PCA_USE_P34P35P36P37() P_SW1 = (P_SW1 & ~0x30) | 0x10 /* ½«PCA/PWMÇл»µ½P34(ECI) P35(CCP0) P36(CCP1) P37(CCP2) */ +#define PCA_USE_P24P25P26P27() P_SW1 = (P_SW1 & ~0x30) | 0x20 /* ½«PCA/PWMÇл»µ½P24(ECI) P25(CCP0) P26(CCP1) P27(CCP2) */ + + +/* 7 6 5 4 3 2 1 0 Reset Value +//sfr CCAPM0 = 0xDA; PWM ¼Ä´æÆ÷ - ECOM0 CCAPP0 CCAPN0 MAT0 TOG0 PWM0 ECCF0 x000,0000 //PCA Ä£¿é0 +//sfr CCAPM1 = 0xDB; PWM ¼Ä´æÆ÷ - ECOM1 CCAPP1 CCAPN1 MAT1 TOG1 PWM1 ECCF1 x000,0000 //PCA Ä£¿é1 +//sfr CCAPM2 = 0xDC; PWM ¼Ä´æÆ÷ - ECOM2 CCAPP2 CCAPN2 MAT2 TOG2 PWM2 ECCF2 x000,0000 //PCA Ä£¿é2 +//sfr CCAPM3 = 0xDD; PWM ¼Ä´æÆ÷ - ECOM3 CCAPP3 CCAPN3 MAT3 TOG3 PWM3 ECCF3 x000,0000 //PCA Ä£¿é3 +;ECOMn = 1: ÔÊÐí±È½Ï¹¦ÄÜ¡£ +;CAPPn = 1: ÔÊÐíÉÏÉýÑØ´¥·¢²¶×½¹¦ÄÜ¡£ +;CAPNn = 1: ÔÊÐíϽµÑØ´¥·¢²¶×½¹¦ÄÜ¡£ +;MATn = 1: µ±Æ¥ÅäÇé¿ö·¢Éúʱ£¬ÔÊÐíCCONÖеÄCCFnÖÃλ¡£ +;TOGn = 1: µ±Æ¥ÅäÇé¿ö·¢Éúʱ£¬CEXn½«·­×ª¡£(CEX0/PCA0/PWM0/P3.7,CEX1/PCA1/PWM1/P3.5) +;PWMn = 1: ½«CEXnÉèÖÃΪPWMÊä³ö¡£ +;ECCFn = 1: ÔÊÐíCCONÖеÄCCFn´¥·¢Öжϡ£ +;ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn +; 0 0 0 0 0 0 0 00H δÆôÓÃÈκι¦ÄÜ¡£ +; x 1 0 0 0 0 x 20H 16λCEXnÉÏÉýÑØ´¥·¢²¶×½¹¦ÄÜ¡£ +; x 0 1 0 0 0 x 10H 16λCEXnϽµÑØ´¥·¢²¶×½¹¦ÄÜ¡£ +; x 1 1 0 0 0 x 30H 16λCEXn/PCAn±ßÑØ£¨ÉÏ¡¢ÏÂÑØ£©´¥·¢²¶×½¹¦ÄÜ¡£ +; 1 0 0 1 0 0 x 48H 16λÈí¼þ¶¨Ê±Æ÷¡£ +; 1 0 0 1 1 0 x 4CH 16λ¸ßËÙÂö³åÊä³ö¡£ +; 1 0 0 0 0 1 0 42H 8λPWM¡£ÎÞÖÐ¶Ï +; 1 1 0 0 0 1 1 63H 8λPWM¡£µÍ±ä¸ß¿É²úÉúÖÐ¶Ï +; 1 0 1 0 0 1 1 53H 8λPWM¡£¸ß±äµÍ¿É²úÉúÖÐ¶Ï +; 1 1 1 0 0 1 1 73H 8λPWM¡£µÍ±ä¸ß»ò¸ß±äµÍ¾ù¿É²úÉúÖÐ¶Ï +;******************************************************************* +;*******************************************************************/ + +#define PCA0_none() CCAPM0 = 0 +#define PCA0_PWM(nbit) CCAPM0 = 0x42,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_PWM_rise_int(nbit) CCAPM0 = 0x63,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_PWM_fall_int(nbit) CCAPM0 = 0x53,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_PWM_edge_int(nbit) CCAPM0 = 0x73,PCA_PWM0 = (PCA_PWM0 & 0x3f) | (nbit<<6) +#define PCA0_capture_rise() CCAPM0 = (0x20 + 1) +#define PCA0_capture_fall() CCAPM0 = (0x10 + 1) +#define PCA0_capture_edge() CCAPM0 = (0x30 + 1) +#define PCA0_16bit_Timer() CCAPM0 = (0x48 + 1) +#define PCA0_High_PulseEnable() CCAPM0 |= 0x04 + +#define PCA1_none() CCAPM1 = 0 +#define PCA1_PWM(nbit) CCAPM1 = 0x42,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_PWM_rise_int(nbit) CCAPM1 = 0x63,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_PWM_fall_int(nbit) CCAPM1 = 0x53,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_PWM_edge_int(nbit) CCAPM1 = 0x73,PCA_PWM1 = (PCA_PWM1 & 0x3f) | (nbit<<6) +#define PCA1_capture_rise() CCAPM1 = (0x20 + 1) +#define PCA1_capture_fall() CCAPM1 = (0x10 + 1) +#define PCA1_capture_edge() CCAPM1 = (0x30 + 1) +#define PCA1_16bit_Timer() CCAPM1 = (0x48 + 1) +#define PCA1_High_PulseEnable() CCAPM1 |= 0x04 + +#define PCA2_none() CCAPM2 = 0 +#define PCA2_PWM(nbit) CCAPM2 = 0x42,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_PWM_rise_int(nbit) CCAPM2 = 0x63,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_PWM_fall_int(nbit) CCAPM2 = 0x53,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_PWM_edge_int(nbit) CCAPM2 = 0x73,PCA_PWM2 = (PCA_PWM2 & 0x3f) | (nbit<<6) +#define PCA2_capture_rise() CCAPM2 = (0x20 + 1) +#define PCA2_capture_fall() CCAPM2 = (0x10 + 1) +#define PCA2_capture_edge() CCAPM2 = (0x30 + 1) +#define PCA2_16bit_Timer() CCAPM2 = (0x48 + 1) +#define PCA2_High_PulseEnable() CCAPM2 |= 0x04 + +//#define PCA3_none() CCAPM3 = 0 +//#define PCA3_PWM(nbit) CCAPM3 = 0x42,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_PWM_rise_int(nbit) CCAPM3 = 0x63,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_PWM_fall_int(nbit) CCAPM3 = 0x53,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_PWM_edge_int(nbit) CCAPM3 = 0x73,PCA_PWM3 = (PCA_PWM3 & 0x3f) | (nbit<<6) +//#define PCA3_capture_rise() CCAPM3 = (0x20 + 1) +//#define PCA3_capture_fall() CCAPM3 = (0x10 + 1) +//#define PCA3_capture_edge() CCAPM3 = (0x30 + 1) +//#define PCA3_16bit_Timer() CCAPM3 = (0x48 + 1) +//#define PCA3_High_PulseEnable() CCAPM3 |= 0x04 + +/**********************************************************/ +typedef unsigned char u8; +typedef unsigned int u16; +typedef unsigned long u32; + +/**********************************************************/ +#define NOP1() _nop_() +#define NOP2() NOP1(),NOP1() +#define NOP3() NOP2(),NOP1() +#define NOP4() NOP3(),NOP1() +#define NOP5() NOP4(),NOP1() +#define NOP6() NOP5(),NOP1() +#define NOP7() NOP6(),NOP1() +#define NOP8() NOP7(),NOP1() +#define NOP9() NOP8(),NOP1() +#define NOP10() NOP9(),NOP1() +#define NOP11() NOP10(),NOP1() +#define NOP12() NOP11(),NOP1() +#define NOP13() NOP12(),NOP1() +#define NOP14() NOP13(),NOP1() +#define NOP15() NOP14(),NOP1() +#define NOP16() NOP15(),NOP1() +#define NOP17() NOP16(),NOP1() +#define NOP18() NOP17(),NOP1() +#define NOP19() NOP18(),NOP1() +#define NOP20() NOP19(),NOP1() +#define NOP21() NOP20(),NOP1() +#define NOP22() NOP21(),NOP1() +#define NOP23() NOP22(),NOP1() +#define NOP24() NOP23(),NOP1() +#define NOP25() NOP24(),NOP1() +#define NOP26() NOP25(),NOP1() +#define NOP27() NOP26(),NOP1() +#define NOP28() NOP27(),NOP1() +#define NOP29() NOP28(),NOP1() +#define NOP30() NOP29(),NOP1() +#define NOP31() NOP30(),NOP1() +#define NOP32() NOP31(),NOP1() +#define NOP33() NOP32(),NOP1() +#define NOP34() NOP33(),NOP1() +#define NOP35() NOP34(),NOP1() +#define NOP36() NOP35(),NOP1() +#define NOP37() NOP36(),NOP1() +#define NOP38() NOP37(),NOP1() +#define NOP39() NOP38(),NOP1() +#define NOP40() NOP39(),NOP1() +#define NOP(N) NOP##N() + + +/**********************************************/ +#define Pin0 0x01 //IOÒý½Å Px.0 +#define Pin1 0x02 //IOÒý½Å Px.1 +#define Pin2 0x04 //IOÒý½Å Px.2 +#define Pin3 0x08 //IOÒý½Å Px.3 +#define Pin4 0x10 //IOÒý½Å Px.4 +#define Pin5 0x20 //IOÒý½Å Px.5 +#define Pin6 0x40 //IOÒý½Å Px.6 +#define Pin7 0x80 //IOÒý½Å Px.7 +#define PinAll 0xFF //IOËùÓÐÒý½Å + +#define P0n_standard(bitn) P0M1 &= ~(bitn), P0M0 &= ~(bitn) /* 00 */ +#define P0n_push_pull(bitn) P0M1 &= ~(bitn), P0M0 |= (bitn) /* 01 */ +#define P0n_pure_input(bitn) P0M1 |= (bitn), P0M0 &= ~(bitn) /* 10 */ +#define P0n_open_drain(bitn) P0M1 |= (bitn), P0M0 |= (bitn) /* 11 */ + +#define P1n_standard(bitn) P1M1 &= ~(bitn), P1M0 &= ~(bitn) +#define P1n_push_pull(bitn) P1M1 &= ~(bitn), P1M0 |= (bitn) +#define P1n_pure_input(bitn) P1M1 |= (bitn), P1M0 &= ~(bitn) +#define P1n_open_drain(bitn) P1M1 |= (bitn), P1M0 |= (bitn) + +#define P2n_standard(bitn) P2M1 &= ~(bitn), P2M0 &= ~(bitn) +#define P2n_push_pull(bitn) P2M1 &= ~(bitn), P2M0 |= (bitn) +#define P2n_pure_input(bitn) P2M1 |= (bitn), P2M0 &= ~(bitn) +#define P2n_open_drain(bitn) P2M1 |= (bitn), P2M0 |= (bitn) + +#define P3n_standard(bitn) P3M1 &= ~(bitn), P3M0 &= ~(bitn) +#define P3n_push_pull(bitn) P3M1 &= ~(bitn), P3M0 |= (bitn) +#define P3n_pure_input(bitn) P3M1 |= (bitn), P3M0 &= ~(bitn) +#define P3n_open_drain(bitn) P3M1 |= (bitn), P3M0 |= (bitn) + +#define P4n_standard(bitn) P4M1 &= ~(bitn), P4M0 &= ~(bitn) +#define P4n_push_pull(bitn) P4M1 &= ~(bitn), P4M0 |= (bitn) +#define P4n_pure_input(bitn) P4M1 |= (bitn), P4M0 &= ~(bitn) +#define P4n_open_drain(bitn) P4M1 |= (bitn), P4M0 |= (bitn) + +#define P5n_standard(bitn) P5M1 &= ~(bitn), P5M0 &= ~(bitn) +#define P5n_push_pull(bitn) P5M1 &= ~(bitn), P5M0 |= (bitn) +#define P5n_pure_input(bitn) P5M1 |= (bitn), P5M0 &= ~(bitn) +#define P5n_open_drain(bitn) P5M1 |= (bitn), P5M0 |= (bitn) + +#define P6n_standard(bitn) P6M1 &= ~(bitn), P6M0 &= ~(bitn) +#define P6n_push_pull(bitn) P6M1 &= ~(bitn), P6M0 |= (bitn) +#define P6n_pure_input(bitn) P6M1 |= (bitn), P6M0 &= ~(bitn) +#define P6n_open_drain(bitn) P6M1 |= (bitn), P6M0 |= (bitn) + +#define P7n_standard(bitn) P7M1 &= ~(bitn), P7M0 &= ~(bitn) +#define P7n_push_pull(bitn) P7M1 &= ~(bitn), P7M0 |= (bitn) +#define P7n_pure_input(bitn) P7M1 |= (bitn), P7M0 &= ~(bitn) +#define P7n_open_drain(bitn) P7M1 |= (bitn), P7M0 |= (bitn) + + +/****************************************************************/ + + +//sfr INT_CLKO = 0x8F; //¸½¼ÓµÄ SFR WAKE_CLKO (µØÖ·£º0x8F) +/* + 7 6 5 4 3 2 1 0 Reset Value + - EX4 EX3 EX2 - T2CLKO T1CLKO T0CLKO 0000,0000B +b6 - EX4 : ÍâÖжÏINT4ÔÊÐí +b5 - EX3 : ÍâÖжÏINT3ÔÊÐí +b4 - EX2 : ÍâÖжÏINT2ÔÊÐí +b2 - T1CLKO : ÔÊÐí T2 Òç³öÂö³åÔÚP3.0½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ +b1 - T1CLKO : ÔÊÐí T1 Òç³öÂö³åÔÚP3.4½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ +b0 - T0CLKO : ÔÊÐí T0 Òç³öÂö³åÔÚP3.5½ÅÊä³ö£¬Fck0 = 1/2 T0 Òç³öÂÊ +*/ + +#define LVD_InterruptEnable() ELVD = 1 +#define LVD_InterruptDisable() ELVD = 0 + + +//sfr WKTCL = 0xAA; //»½ÐѶ¨Ê±Æ÷µÍ×Ö½Ú +//sfr WKTCH = 0xAB; //»½ÐѶ¨Ê±Æ÷¸ß×Ö½Ú +// B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 +// WKTEN S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 n * 560us +#define WakeTimerDisable() WKTCH &= 0x7f /* WKTEN = 0 ½ûֹ˯Ãß»½ÐѶ¨Ê±Æ÷ */ +#define WakeTimerSet(scale) WKTCL = (scale) % 256,WKTCH = (scale) / 256 | 0x80 /* WKTEN = 1 ÔÊÐí˯Ãß»½ÐѶ¨Ê±Æ÷ */ + + + +//sfr BUS_SPEED = 0xA1; //Stretch register - - - - - - EXRTS1 EXRTSS0 xxxx,xx10 +#define BUS_SPEED_1T() BUS_SPEED = BUS_SPEED & ~3 +#define BUS_SPEED_2T() BUS_SPEED = (BUS_SPEED & ~3) | 1 +#define BUS_SPEED_4T() BUS_SPEED = (BUS_SPEED & ~3) | 2 +#define BUS_SPEED_8T() BUS_SPEED = (BUS_SPEED & ~3) | 3 + +#define BUS_RD_WR_P44_P43() BUS_SPEED = BUS_SPEED & 0x3f +#define BUS_RD_WR_P37_P36() BUS_SPEED = (BUS_SPEED & 0x3f) | 0x40 +#define BUS_RD_WR_P42_P40() BUS_SPEED = (BUS_SPEED & 0x3f) | 0x80 + + +/* interrupt vector */ +#define INT0_VECTOR 0 +#define TIMER0_VECTOR 1 +#define INT1_VECTOR 2 +#define TIMER1_VECTOR 3 +#define UART1_VECTOR 4 +#define ADC_VECTOR 5 +#define LVD_VECTOR 6 +#define PCA_VECTOR 7 +#define UART2_VECTOR 8 +#define SPI_VECTOR 9 +#define INT2_VECTOR 10 +#define INT3_VECTOR 11 +#define TIMER2_VECTOR 12 +#define INT4_VECTOR 16 +#define UART3_VECTOR 17 +#define UART4_VECTOR 18 +#define TIMER3_VECTOR 19 +#define TIMER4_VECTOR 20 +#define CMP_VECTOR 21 +#define PWM0_VECTOR 22 +#define PWMFD_VECTOR 23 +#define I2C_VECTOR 24 +#define USB_VECTOR 25 +#define PWMA_VECTOR 26 +#define PWMB_VECTOR 27 +#define PWM1_VECTOR 28 +#define PWM2_VECTOR 29 +#define PWM3_VECTOR 30 +#define PWM4_VECTOR 31 +#define PWM5_VECTOR 32 + + +#define TRUE 1 +#define FALSE 0 + +//============================================================= + +//======================================== + +#define Priority_0 0 //ÖжÏÓÅÏȼ¶Îª 0 ¼¶£¨×îµÍ¼¶£© +#define Priority_1 1 //ÖжÏÓÅÏȼ¶Îª 1 ¼¶£¨½ÏµÍ¼¶£© +#define Priority_2 2 //ÖжÏÓÅÏȼ¶Îª 2 ¼¶£¨½Ï¸ß¼¶£© +#define Priority_3 3 //ÖжÏÓÅÏȼ¶Îª 3 ¼¶£¨×î¸ß¼¶£© + +//======================================== + +#define ENABLE 1 +#define DISABLE 0 + +#endif diff --git a/myinc/config.h b/myinc/config.h new file mode 100644 index 0000000..1518746 --- /dev/null +++ b/myinc/config.h @@ -0,0 +1,33 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* ���Ҫ�ڳ�����ʹ�ô˴���,���ڳ�����ע��ʹ����STC�����ϼ����� */ +/*---------------------------------------------------------------------*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*********************************************************/ + +//#define MAIN_Fosc 22118400L //������ʱ�� +//#define MAIN_Fosc 12000000L //������ʱ�� +#define MAIN_Fosc 11059200L //������ʱ�� +//#define MAIN_Fosc 5529600L //������ʱ�� +// #define MAIN_Fosc 24000000L //������ʱ�� + + +#define STC8Hxx //STC8Hϵ�� +//#define STC8Gxx //STC8Gϵ�� + +/*********************************************************/ + +#include "STC8xxxx.H" + + +#endif diff --git a/myinc/timer.h b/myinc/timer.h new file mode 100644 index 0000000..d7909b3 --- /dev/null +++ b/myinc/timer.h @@ -0,0 +1,47 @@ +/*---------------------------------------------------------------------*/ +/* --- STC MCU Limited ------------------------------------------------*/ +/* --- STC 1T Series MCU Demo Programme -------------------------------*/ +/* --- Mobile: (86)13922805190 ----------------------------------------*/ +/* --- Fax: 86-0513-55012956,55012947,55012969 ------------------------*/ +/* --- Tel: 86-0513-55012928,55012929,55012966 ------------------------*/ +/* --- Web: www.STCMCU.com --------------------------------------------*/ +/* --- Web: www.STCMCUDATA.com ---------------------------------------*/ +/* --- QQ: 800003751 -------------------------------------------------*/ +/* ���Ҫ�ڳ�����ʹ�ô˴���,���ڳ�����ע��ʹ����STC�����ϼ����� */ +/*---------------------------------------------------------------------*/ + +#ifndef __TIMER_H +#define __TIMER_H + +#include "config.h" + +#define Timer0 0 +#define Timer1 1 +#define Timer2 2 +#define Timer3 3 +#define Timer4 4 + +#define TIM_16BitAutoReload 0 +#define TIM_16Bit 1 +#define TIM_8BitAutoReload 2 +#define TIM_16BitAutoReloadNoMask 3 + +#define TIM_CLOCK_1T 0 +#define TIM_CLOCK_12T 1 +#define TIM_CLOCK_Ext 2 + +typedef struct +{ + u8 TIM_Mode; // ����ģʽ, TIM_16BitAutoReload,TIM_16Bit,TIM_8BitAutoReload,TIM_16BitAutoReloadNoMask + u8 TIM_Priority; // ���ȼ����� Priority_0,Priority_1,Priority_2,Priority_3 + u8 TIM_Interrupt; // ����� ENABLE,DISABLE + u8 TIM_ClkSource; // ʱ��Դ TIM_CLOCK_1T,TIM_CLOCK_12T,TIM_CLOCK_Ext + u8 TIM_ClkOut; // �ɱ��ʱ�����, ENABLE,DISABLE + u16 TIM_Value; // װ�س�ֵ + u8 TIM_Run; // �Ƿ����� ENABLE,DISABLE +} TIM_InitTypeDef; + +u8 Timer_Inilize(u8 TIM, TIM_InitTypeDef *TIMx); +extern u8 KILL_time; +void Timer_config(void); +#endif